AD9748 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9748 Datasheet PDF : 20 Pages
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AD9748
DYNAMIC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, Differential
Single-Ended Output, 50 ⍀ Doubly Terminated, unless otherwise noted.)
Parameter
Min
Typ
Max
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)2
Output Noise (IOUTFS = 2 mA)2
165
11
1
5
2.5
2.5
50
30
AC LINEARITY
Signal-to-Noise and Distortion Ratio
fCLOCK = 50 MSPS; fOUT = 5 MHz
fCLOCK = 50 MSPS; fOUT = 19 MHz
fCLOCK = 100 MSPS; fOUT = 5 MHz
fCLOCK = 100 MSPS; fOUT = 39 MHz
fCLOCK = 165 MSPS; fOUT = 5 MHz
fCLOCK = 165 MSPS; fOUT = 49 MHz
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1 MHz
fCLOCK = 50 MSPS; fOUT = 12.5 MHz
fCLOCK = 100 MSPS; fOUT = 25 MHz
fCLOCK = 165 MSPS; fOUT = 41.3 MHz
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1 MHz
0 dBFS Output
fCLOCK = 65 MSPS; fOUT = 5 MHz
fCLOCK = 65 MSPS; fOUT = 19 MHz
fCLOCK = 100 MSPS; fOUT = 5 MHz
fCLOCK = 100 MSPS; fOUT = 39 MHz
fCLOCK = 165 MSPS; fOUT = 5 MHz
fCLOCK = 165 MSPS; fOUT = 49 MHz
50
47
50
46
50
47
–72
–61
–65
–60
–58
61
72
69
65
68
62
68
54
NOTES
1Measured single-ended into 50 W load.
2Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
Specifications subject to change without notice.
Unit
MSPS
ns
ns
pV-s
ns
ns
pA/÷Hz
pA/÷Hz
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
CLK INPUTS*
Input Voltage Range
Common-Mode Voltage
Differential Voltage
2.1
3
0
–10
–10
5
2.0
1.5
1.5
V
0.9
V
+10
mA
+10
mA
pF
ns
ns
ns
0
3
V
0.75
1.5
2.25
V
0.5
1.5
V
*Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
Specifications subject to change without notice.
REV. 0
–3–
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