AD9748 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9748

8-Bit, 165 MSPS TxDAC® D/A Converter

Analog Devices 

AD9748

REFERENCE CONTROL AMPLIFIER

The AD9748 contains a control amplifier that is used to regulate

the full-scale output current, IOUTFS. The control amplifier is

configured as a V-I converter, as shown in Figure 4, so that its

current output, IREF, is determined by the ratio of the VREFIO

and an external resistor, RSET, as stated in Equation 4. IREF is

copied to the segmented current sources with the proper scale

factor to set IOUTFS as stated in Equation 3.

The control amplifier allows a wide (10:1) adjustment span

of IOUTFS over a 2 mA to 20 mA range by setting IREF between

62.5 mA and 625 mA. The wide adjustment span of IOUTFS pro-

vides several benefits. The first relates directly to the power

dissipation of the AD9748, which is proportional to IOUTFS (refer

to the Power Dissipation section). The second relates to the 20 dB

adjustment, which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 500 kHz and can be used for low frequency small

signal multiplying applications.

DAC TRANSFER FUNCTION

Both DACs in the AD9748 provide complementary current outputs,

IOUTA and IOUTB. IOUTA will provide a near full-scale cur-

rent output, IOUTFS, when all bits are high (i.e., DAC CODE = 255)

while IOUTB, the complementary output, provides no current.

The current output appearing at IOUTA and IOUTB is a func-

tion of both the input code and IOUTFS and can be expressed as:

IOUTA = (DAC CODE / 256) ¥ IOUTFS

(1)

IOUTB = (255 – DAC CODE) / 256 ¥ IOUTFS

(2)

where DAC CODE = 0 to 255 (i.e., decimal representation).

As mentioned previously, IOUTFS is a function of the reference

current IREF, which is nominally set by a reference voltage, VREFIO,

and external resistor, RSET. It can be expressed as:

IOUTFS = 32 ¥ IREF

(3)

where

IREF = VREFIO / RSET

(4)

The two current outputs will typically drive a resistive load directly

or via a transformer. If dc coupling is required, IOUTA and

IOUTB should be directly connected to matching resistive loads,

RLOAD, that are tied to analog common, ACOM. Note, RLOAD

may represent the equivalent load resistance seen by IOUTA or

IOUTB as would be the case in a doubly terminated 50 W or

75 W cable. The single-ended voltage output appearing at the

IOUTA and IOUTB nodes is simply:

VOUTA = IOUTA ¥ RLOAD

(5)

VOUTB = IOUTB ¥ RLOAD

(6)

Note that the full-scale value of VOUTA and VOUTB should not

exceed the specified output compliance range to maintain speci-

fied distortion and linearity performance.

VDIFF = (IOUTA – IOUTB) ¥ RLOAD

(7)

Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can

be expressed as:

{ } VDIFF = (2 ¥ DAC CODE – 255) / 256

( ) 32 ¥ RLOAD /RSET ¥ VREFIO

(8)

These last two equations highlight some of the advantages of

operating the AD9748 differentially. First, the differential opera-

tion will help cancel common-mode error sources associated

with IOUTA and IOUTB, such as noise, distortion, and dc offsets.

Second, the differential code dependent current and subsequent

voltage, VDIFF, is twice the value of the single-ended voltage

output (i.e., VOUTA or VOUTB), thus providing twice the signal

power to the load.

Note that the gain drift temperature performance for a single-

ended (VOUTA and VOUTB) or differential output (VDIFF) of the

AD9748 can be enhanced by selecting temperature tracking

resistors for RLOAD and RSET due to their ratiometric relationship

as shown in Equation 8.

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA, and

IOUTB, may be configured for single-ended or differential opera-

tion. IOUTA and IOUTB can be converted into complementary

single-ended voltage outputs, VOUTA and VOUTB, via a load resistor,

RLOAD, as described in the DAC Transfer Function section by

Equations 5 through 8. The differential voltage, VDIFF, existing

between VOUTA and VOUTB, can also be converted to a single-

ended voltage via a transformer or differential amplifier configuration.

The ac performance of the AD9748 is optimum and specified

using a differential transformer coupled output in which the

voltage swing at IOUTA and IOUTB is limited to ± 0.5 V.

The distortion and noise performance of the AD9748 can be

enhanced when it is configured for differential operation. The

common-mode error sources of both IOUTA and IOUTB can

be significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode error

sources include even-order distortion products and noise. The

enhancement in distortion performance becomes more signifi-

cant as the frequency content of the reconstructed waveform

increases and/or its amplitude decreases. This is due to the first

order cancellation of various dynamic common-mode distortion

mechanisms, digital feedthrough, and noise.

Performing a differential-to-single-ended conversion via a trans-

former also provides the ability to deliver twice the reconstructed

signal power to the load (assuming no source termination). Since

the output currents of IOUTA and IOUTB are complementary,

they become additive when processed differentially. A properly

selected transformer will allow the AD9748 to provide the required

power and voltage levels to different loads.

The output impedance of IOUTA and IOUTB is determined by the

equivalent parallel combination of the PMOS switches associ-

ated with the current sources and is typically 100 kW in parallel

with 5 pF. It is also slightly dependent on the output voltage

(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.

As a result, maintaining IOUTA and/or IOUTB at a virtual

ground via an I-V op amp configuration will result in the optimum

dc linearity. Note that the INL/DNL specifications for the AD9748

are measured with IOUTA maintained at a virtual ground via

an op amp.

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of –1.0 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a breakdown

of the output stage and affect the reliability of the AD9748.

REV. 0

–9–

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