AD9814S View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9814S Datasheet PDF : 8 Pages
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AD9814S
6.0 Table I. Electrical Table:
Parameter
See notes at end of table
RESOLUTION
Supply Currents
Power dissipation
Power supply rejection
ACCURACY (Entire Signal Path)
Integral Nonlinearity 2/
ACCURACY (Entire Signal Path)
Differential Nonlinearity
ACCURACY (Entire Signal Path)
Offset Error
ACCURACY (Entire Signal Path)
Gain Error 3/
PGA Gain Ratio 4/
Table I
Symbol
RES
Conditions 1/
Unless Otherwise Specified
No Missing Codes
Sub
Group
1,2,3
Limit Min
14
Limit Max
IAVDD
IDRVDD
PD
PSR AVDD= +5.0V ± 0.25V
INL
DNL
VOS
1,2,3
80
1,2,3
10
1,2,3
450
1,2
0.3
3
0.5
1,2
-11
11
3
-18
11
1
-1
1.25
2
-1
1
3
-1
1.5
1,2,3
-104
104
Units
Bits
mA
mA
mW
%FSR
%FSR
LSB
LSB
LSB
LSB
LSB
mV
GAIN
1,2,3
-5.3
5.3
%FSR
PGA GAIN
1,2,3
5.7
5.9
DIFFERENTIAL VREF
CAPT-CAPB (4V Input Range)
VREF4
1,2,3
1.9
2.1
V
DIFFERENTIAL VREF
CAPT-CAPB (2V Input Range)
VREF2
1,2,3
0.94
1.06
V
TABLE I NOTES:
1/ TA = +25 °C, TA Max = +125 °C, TA Min = -55 °C. AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS, FADCCLK = 6 MHz, FCDSCLK1 = FCDSCLK2 = 2
MHz, PGA Gain = 1, Input Range = 4V, unless otherwise noted.
2/ INL is measured using the “fixed endpoint” method, NOT using a “best-fit” calculation.
3/ The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.
4/ The PGA Gain is approximately “linear in dB” and follows the equation: PGA Gain = (5.8 / (1 + 4.8 (63 – G) / 63)) where G is the register
value.
ASD0016515 Rev. D | Page 4 of 7
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