AD9838 View Datasheet(PDF) - Analog Devices
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Description
Manufacturer
AD9838 Datasheet PDF : 32 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9838
AVDD 1
DVDD 2
CAP/2.5V 3
DGND 4
MCLK 5
AD9838
TOP
VIEW
(Not to Scale)
15 AGND
14 VIN
13 SIGN BIT OUT
12 FSYNC
11 SCLK
NOTES
1. CONNECT EXPOSED PAD TO GROUND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
AVDD
Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between AVDD and AGND.
2
DVDD
Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between DVDD and DGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator when DVDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If DVDD is less than or equal to 2.7 V, CAP/2.5V should be shorted to DVDD.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSEL bit. When
the FSEL bit is used to select the frequency register, the FSELECT pin should be tied to CMOS high or low.
7
PSELECT
Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator
output. The phase register to be used can be selected using the PSELECT pin or the PSEL bit. When the PSEL bit
is used to select the phase register, the PSELECT pin should be tied to CMOS high or low.
8
RESET
Active High Digital Input. This pin resets the appropriate internal registers to 0 (this corresponds to an analog
output of midscale). RESET does not affect any of the addressable registers.
9
SLEEP
Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as
the SLEEP12 control bit.
10
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
11
SCLK
Serial Clock Input. Data is clocked into the AD9838 on each falling edge of SCLK.
12
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken
low, the internal logic is informed that a new word is being loaded into the device.
13
SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be
output on this pin. Setting the OPBITEN bit in the control register to 1 enables this output pin. The SIGN/PIB bit
determines whether the comparator output or the MSB from the NCO is output on this pin.
14
VIN
Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output.
The DAC output should be filtered appropriately before it is applied to the comparator to reduce jitter. When
the OPBITEN and SIGN/PIB bits in the control register are set to 1, the comparator input is connected to VIN.
15
AGND
Analog Ground.
16, 17
IOUT,
IOUTB
Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected
between IOUT and AGND. IOUTB should be tied to AGND through an external load resistor of 200 Ω, but it can
be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough.
Rev. A | Page 7 of 32
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