AD9845AJST View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD9845AJST Datasheet PDF : 22 Pages
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AD9845A
DEFINITIONS OF SPECIFICATIONS
in LSB, and represents the rms noise level of the total signal
DIFFERENTIAL NONLINEARITY (DNL)
chain at the specified gain setting. The output noise can be
An ideal ADC exhibits code transitions that are exactly 1 LSB
converted to an equivalent voltage, using the relationship 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code = (ADC Full Scale/2N codes) when N is the bit resolution of the
must have a finite width. No missing codes guaranteed to 12-bit ADC. For the AD9845A, 1 LSB is 500 µV.
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
PEAK NONLINEARITY
pins. This represents a very high frequency disturbance on the
Peak nonlinearity, a full signal chain specification, refers to the
AD984x’s power supply. The PSR specification is calculated
peak deviation of the output of the AD984x from a true straight from the change in the data outputs for a given step change in
line. The point used as “zero scale” occurs 1/2 LSB before the
the supply voltage.
first code transition. “Positive full scale” is defined as a Level 1,
OBSOLETE 1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD984x
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
DVDD
ACVDD
330⍀
60⍀
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DRVDD
DATA
THREE-
STATE
DOUT
RNW
DVSS
DRVSS
Figure 2. Data Outputs—D0–D11
REV. 0
–7–
ACVSS
ACVSS
Figure 3. CCDIN (Pin 30)
DVDD
DATA IN
DATA OUT
DVDD
330⍀
DVSS
DVSS
DVSS
Figure 4. SDATA (Pin 47)
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