AD9845AJST View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9845AJST

Mixed-Signal Front-End (MxFE) Processor for Broadband Communications

Analog Devices 

CCD-MODE AND AUX MODE TIMING

AD9845A

CCD

SIGNAL

N

tID

N+1

N+2

tID

N+9

N+10

SHP

tS1

tS2

tCP

SHD

tINH

DATACLK

OBSOLETE tOD

tH

OUTPUT

N–10

N–9

N–8

DATA

N–1

N

NOTES:

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

Figure 5. CCD-Mode Timing

CCD

SIGNAL

EFFECTIVE PIXELS

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS

EFFECTIVE PIXELS

CLPOB

CLPDM

PBLK

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

DUMMY BLACK

EFFECTIVE DATA

NOTES:

1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.

Figure 6. Typical CCD-Mode Line Clamp Timing

VIDEO

SIGNAL

DATACLK

OUTPUT

DATA

REV. 0

N

N+1

N+9

N+8

tID

N+2

tCP

tOD

N–10

tH

N–9

N–8

N–1

N

Figure 7. AUX-Mode Timing

–9–

Share Link: