AD9863 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9863

Mixed-Signal Front-End (MxFE™) Baseband Transceiver for Broadband Applications

Analog Devices 

AD9863

TIMING SPECIFICATIONS

Table 5.

Parameter

INPUT CLOCK

CLKIN2 Clock Rate (PLL Bypassed)

PLL Input Frequency

PLL Ouput Frequency

TxPATH DATA

Setup Time

(HD24 Mode, Time Required before Data Latching Edge)

Temp Test Level

Full

IV

Full

IV

Full

IV

Full

V

Hold Time

(HD24 Mode, Time Required after Data Latching Edge)

Full

V

Latency 1× Interpolation (Data In until Peak Output Response) Full

V

Latency 2× Interpolation (Data In until Peak Output Response) Full

V

Latency 4× Interpolation (Data In until Peak Output Response) Full

V

RxPATH DATA

Output Delay (HD24 Mode, tOD)

Full

V

Latency

Full

V

Min Typ Max Unit

1

200 MHz

16

200 MHz

32

350 MHz

5

ns (see Clock

Distribution Block

section)

–1.5

ns (see Clock

Distribution Block

section)

7

DAC Clock Cycles

35

DAC Clock Cycles

83

DAC Clock Cycles

–1.5

ns ( see Clock

Distribution Block

section)

5

ADC Clock Cycles

Table 6. Explanation of Test Levels

Level Description

I

100% production tested.

II

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. 0 | Page 6 of 40

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