AD9927 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9927

14-Bit CCD Signal Processor with V-Driver and Precision Timing™ Generator

Analog Devices 

AD9927

VERTICAL DRIVER SPECIFICATIONS

VH1, VH2 = 15 V. VM1, VM2, VMM = 0 V. VL1, VL2, VLL = −7.5 V. CL shown in load model, 25°C.

Table 5.

Parameter

V-DRIVER OUTPUTS (SIMPLIFIED LOAD CONDITIONS, 3000 pF to GROUND)

Delay Time, VL to VM and VM to VH

Delay Time, VM to VL and VH to VM

Rise Time, VL to VM

Rise Time, VM to VH

Fall Time, VM to VL

Fall Time, VH to VM

Output Currents

@ −7.25 V

@ −0.25 V

@ +0.25 V

@ +14.75 V

RON

SUBCK OUTPUT (SIMPLIFIED LOAD CONDITIONS, 1000 pF to GROUND)

Delay Time, VLL to VH

Delay Time, VH to VLL

Delay Time, VLL to VMM

Delay Time, VMM to VH

Delay Time, VH to VMM

Delay Time, VMM to VLL

Rise Time, VLL to VH

Rise Time, VLL to VMM

Rise Time, VMM to VH

Fall Time, VH to VLL

Fall Time, VH to VMM

Fall Time, VMM to VLL

Output Currents

@ −7.25 V

@ −0.25 V

@ +0.25 V

@ +14.75 V

RON

Symbol

tPLM, tPMH

tPML, tPHM

tRLM

tRMH

tFML

tFHM

tPLH

tPHL

tPLM

tPMH

tPHM

tPML

tRLH

tRLM

tRMH

tFHL

tFHM

tFML

Min

Typ

Max

Unit

35

ns

35

ns

125

ns

260

ns

220

ns

125

ns

10

mA

−22

mA

22

mA

−10

mA

35

Ω

25

ns

30

ns

25

ns

25

ns

30

ns

25

ns

40

ns

45

ns

30

ns

40

ns

90

ns

25

ns

20

mA

−12

mA

12

mA

−20

mA

35

Ω

V-DRIVER

INPUT

50%

50%

V-DRIVER

OUTPUT

tRLM, tRMH, tRLH

90%

tPML, tPHM, tPHL

90%

tPLM, tPMH, tPLH

10%

tFML, tFHM, tFHL

10%

Figure 2. Definition of V-Driver Timing Specifications

Rev. 0 | Page 7 of 100

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