AD9984AKSTZ-170 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9984AKSTZ-170

500 MSPS Direct Digital Synthesizer

Analog Devices 

AD9984A

SYNC PROCESSING

The inputs of the sync processing section of the AD9984A are

combinations of digital Hsyncs and Vsyncs, analog sync-on-

green or sync-on-Y signals, and an optional external coast

signal. From these signals, the part generates a precise, jitter-

free clock from its PLL, an odd/even-field signal, HSOUT and

VSOUT signals, a count of Hsyncs per Vsync, and a

programmable SOGOUT. The main sync processing blocks are

the sync slicer, sync separator, Hsync filter, Hsync regenerator,

Vsync filter, and coast generator.

• The sync slicer extracts the sync signal from the green

graphics or luminance video signal that is connected to

the SOGINx inputs, and outputs a digital composite sync.

• The sync separator extracts Vsync from the composite sync

signal, which can come from either the sync slicer or the

HSYNCx inputs.

• The Hsync filter is used to eliminate any extraneous pulses

from the HSYNCx or SOGINx inputs, outputting a clean,

low-jitter signal that is appropriate for mode detection and

clock generation.

• The Hsync regenerator is used to recreate a clean, although

not low jitter, Hsync signal that can be used for mode

detection and counting Hsyncs per Vsync.

• The Vsync filter is used to eliminate spurious Vsyncs, main-

tain a stable timing relationship between the Vsync and Hsync

output signals, and generate the odd/even field output.

• The coast generator creates a robust coast signal to allow the

PLL to maintain its frequency in the absence of Hsync pulses.

HSYNC0

AD9984A

CHANNEL

SELECT

0x1E:6

HSYNC

SELECT

0x12:6

HSYNC1

ACTIVITY

DETECT

POLARITY

DETECT

MUX

MUX

HSYNC FILTER

AND

REGENERATOR

SOGIN0

SOGIN1

ACTIVITY POLARITY

DETECT

DETECT

SYNC SLICER

ACTIVITY

DETECT

SYNC SLICER

MUX

FILTERED

HSYNC

SP SYNC

FILTER EN

0x20:1

REGENERATED

HSYNC

MUX

SET

POLARITY

SOGOUT

VSYNC0

VSYNC1

ACTIVITY

DETECT

ACTIVITY

DETECT

POLARITY

DETECT

VSYNC

MUX

MUX

SOGOUT

SELECT

0x1D:1,0

VSYNC

FILTERED VSYNC

VSOUT/A0

ACTIVITY POLARITY

DETECT

DETECT

EXTCK/COAST

VSYNC

FILTER EN

0x14:2

MUX

PLL SYNC

FILTER EN

0x20:2

MUX

HSYNC

COAST

MUX

PLL CLOCK

GENERATOR

COAST SELECT

0x18:7

VSYNC FILTER EN

0x14:2

HSYNC/VSYNC

COUNTER

REG 0x26,

SET

POLARITY

0x27

SET

POLARITY

O/E FIELD

HSOUT

SET

POLARITY

DATACK

Figure 9. Sync Processing Block Diagram

Rev. 0 | Page 16 of 44

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