ADAU1761 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADAU1761 Datasheet PDF : 92 Pages
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ADAU1761
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V ± 10%.
Table 7. Digital Timing
Parameter
MASTER CLOCK
tMP
tMP
tMP
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
DIGITAL MICROPHONE
tDCF
tDCR
tDDV
tDDH
Limit
tMIN
tMAX
Unit
Description
74
488
ns
37
244
ns
24.7
162.7
ns
18.5
122
ns
MCLK period, 256 × fS mode.
MCLK period, 512 × fS mode.
MCLK period, 768 × fS mode.
MCLK period, 1024 × fS mode.
5
ns
BCLK pulse width low.
5
ns
BCLK pulse width high.
5
ns
LRCLK setup. Time to BCLK rising.
5
ns
LRCLK hold. Time from BCLK rising.
5
ns
DAC_SDATA setup. Time to BCLK rising.
5
ns
DAC_SDATA hold. Time from BCLK rising.
50
ns
ADC_SDATA delay. Time from BCLK falling in master mode.
10
MHz
CCLK frequency.
10
ns
CCLK pulse width low.
10
ns
CCLK pulse width high.
5
ns
CLATCH setup. Time to CCLK rising.
10
ns
CLATCH hold. Time from CCLK rising.
10
ns
CLATCH pulse width high.
5
ns
CDATA setup. Time to CCLK rising.
5
ns
CDATA hold. Time from CCLK rising.
50
ns
COUT three-stated. Time from CLATCH rising.
400
kHz
SCL frequency.
0.6
μs
SCL high.
1.3
μs
SCL low.
0.6
μs
Setup time; relevant for repeated start condition.
0.6
μs
Hold time. After this period, the first clock is generated.
100
ns
Data setup time.
300
ns
SCL rise time.
300
ns
SCL fall time.
300
ns
SDA rise time.
300
ns
SDA fall time.
0.6
μs
Bus-free time. Time between stop and start.
RLOAD = 1 MΩ, CLOAD = 14 pF.
10
ns
Digital microphone clock fall time.
10
ns
Digital microphone clock rise time.
22
30
ns
Digital microphone delay time for valid data.
0
12
ns
Digital microphone delay time for data three-stated.
Rev. C | Page 11 of 92
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