ADAU1761 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADAU1761 Datasheet PDF : 92 Pages
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ADAU1761
SPECIFICATIONS
Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement
bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V,
unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase
deviation specifications.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
Test Conditions/Comments
Min
ANALOG-TO-DIGITAL CONVERTERS
ADC performance excludes mixers
and PGA
ADC Resolution
All ADCs
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
Single-Ended Line Input
−12 dB gain
0 dB gain
6 dB gain
PGA Inverting Inputs
−12 dB gain
0 dB gain
35.25 dB gain
PGA Noninverting Inputs
All gains
SINGLE-ENDED LINE INPUT
Full-Scale Input Voltage (0 dB)
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
Dynamic Range
20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
No Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
Total Harmonic Distortion + Noise −1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
No Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
Gain per Step
Total Gain Range
−12
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
CM capacitor = 20 μF
100 mV p-p @ 217 Hz
100 mV p-p @ 1 kHz
Typ
Max
24
0.375
95
83
21
10.5
84.5
53
2
105
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
94
99
91
96
−88
−90
94
99
91
96
3
+6
−87
0.005
0
−12
68
65
67
Unit
Bits
dB
dB
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
dB
dB
dB
Rev. C | Page 4 of 92
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