ADC0808S125 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

ADC0808S125

Single 8-bit ADC, up to 125 MHz or 250 MHz

Integrated Device Technology 

Integrated Device Technology

ADC0808S125/250

Single 8-bit ADC, up to 125 MHz or 250 MHz

11. Dynamic characteristics

Table 13. Dynamic characteristics

VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;

Tamb = 40 C to +85 C; Vi(IN)  Vi(INN) = 2.0 V  0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at

VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified.

Symbol Parameter

Conditions

Min Typ Max Unit

Clock timing input: pins CLK+ and CLK

fclk(min)

minimum clock frequency

fclk(max)

maximum clock frequency

tw(clk)

clock pulse width

fclk = 125 MHz

Timing output: pins D0 to D7 and IR[1]; see Figure 5

-

-

250 -

1.8

-

1

MHz

-

MHz

-

ns

td(s)

sampling delay time

1.8 V CMOS clock

LVDS clock

-

1.3

-

ns

-

1.65 -

ns

th(o)

output hold time

1.8 V CMOS clock

LVDS clock

3.3

4.4

-

ns

4.2

4.8

-

ns

td(o)

output delay time

1.8 V CMOS clock

LVDS clock

-

5.4

6.9

ns

-

5.8

7.3

ns

Timing complete conversion signal: pin CCS; see Figure 6

fCCS(max)

td(CCS)

maximum CCS frequency

CCS delay time

DEL0 = HIGH; DEL1 = LOW

DEL0 = LOW; DEL1 = HIGH

125 -

-

-

0.3

-

-

0.8

-

MHz

ns

ns

DEL0 = HIGH; DEL1 = HIGH

-

1.9

-

ns

3-state output delay time: pins CCS, IR and D7 to D0

tdZH

float to active HIGH delay time

tdZL

float to active LOW delay time

tdHZ

active HIGH to float delay time

tdLZ

active LOW to float delay time

Analog signal processing (50 % clock duty factor); see Section 12

-

2.1

-

ns

-

2.2

-

ns

-

3.3

-

ns

-

2.9

-

ns

INL

DNL

integral non-linearity

differential non-linearity

fclk = 20 MHz; fi = 21.4 MHz

-

0.82 -

LSB

fclk = 20 MHz; fi = 21.4 MHz; no

-

0.4 -

LSB

missing code guaranteed

EO

offset error

EG

gain error

B

bandwidth

VCCA = 3.3 V; VCCD = 1.8 V;

-

Tamb = 25 C; output code = 127

spread from device to device;

-

VCCA = 3.3 V; VCCD = 1.8 V;

Tamb = 25 C

fclk = 125 MHz; 3 dB; full-scale [2] -

input

2.5

-

1.85 -

560 -

mV

%

MHz

THD

total harmonic distortion

Nth(RMS)

S/N

RMS thermal noise

signal-to-noise ratio

fclk = 125 MHz; fi = 78 MHz

[3] -

53 -

dB

fclk = 250 MHz; fi = 125 MHz

-

53 -

dB

shorted input; fclk = 125 MHz

-

0.5

-

LSB

fclk = 125 MHz; fi = 78 MHz

[4] -

48

-

dBc

fclk = 250 MHz; fi = 125 MHz

-

47

-

dBc

ADC0808S125_ADC0808S250_4

Product data sheet

Rev. 04 — 2 July 2012

© IDT 2012. All rights reserved.

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