EV-ADF4157SD1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EV-ADF4157SD1Z Datasheet PDF : 24 Pages
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ADF4157
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
RSET 1
CP 2
CPGND 3
AGND 4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
ADF4157
TOP VIEW
(Not to Scale)
16 VP
15 DVDD
14 MUXOUT
13 LE
12 DATA
11 CLK
10 CE
9 DGND
Figure 3. TSSOP Pin Configuration
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
ADF4157
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE.
THIS PAD SHOULD BE CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
1
19
RSET
2
20
CP
3
1
CPGND
4
2, 3
AGND
5
4
RFINB
6
5
RFINA
7
6, 7
AVDD
8
8
REFIN
9
9, 10
DGND
10
11
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
Description
Connecting a resistor between this pin and ground sets the maximum charge pump output
current.
The relationship between ICP and RSET is
25.5
ICPMAX RSET
where:
RSET = 5.1 kΩ.
ICPMAX = 5 mA.
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which, in
turn, drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF.
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have
the same voltage as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the input shift register on the CLK rising edge. This input is a high impedance
CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the input shift register is loaded
into one of the five latches, with the latch selected using the control bits.
This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
Rev. D | Page 6 of 24
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