ADF7021-V View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADF7021-V Datasheet PDF : 60 Pages
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ADF7021-V
GENERAL SPECIFICATIONS
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE RANGE (TA)
−40
+85
°C
POWER SUPPLIES
Voltage Supply, VDD
2.3
3.6
V
All VDDx pins must be tied together
TRANSMIT CURRENT CONSUMPTION1, 2
VDD = 3.0 V, PA is matched into 50 Ω
868 MHz
0 dBm
17.6
mA
5 dBm
20.8
mA
10 dBm
27.1
mA
460 MHz
0 dBm
13.8
mA
5 dBm
17
mA
10 dBm
23
mA
RECEIVE CURRENT CONSUMPTION2
VDD = 3.0 V
868 MHz
Low Current Mode
19.3
mA
High Sensitivity Mode
21.7
mA
460 MHz
Low Current Mode
16.3
mA
High Sensitivity Mode
18.3
mA
POWER-DOWN CURRENT CONSUMPTION2
Low Power Sleep Mode
0.1
1
μA
CE low
1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards.
Improved PA efficiency is achieved by using a separate PA matching network.
2 Device current only. VCO and TCXO currents are excluded.
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, GND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 6.
Parameter
t1
t2
t3
t4
t5
t6
t8
t9
t10
t11
t12
t13
t14
t15
Limit at TMIN to TMAX
>10
>10
>25
>25
>10
>20
<25
<25
>10
5 < t11 < (¼ × tBIT)
>5
>5
5 < t14 < (¼ × tBIT)
>¼ × tBIT
Unit
Description
ns
SDATA to SCLK setup time
ns
SDATA to SCLK hold time
ns
SCLK high duration
ns
SCLK low duration
ns
SCLK to SLE setup time
ns
SLE pulse width
ns
SCLK to SREAD data valid, readback
ns
SREAD hold time after SCLK, readback
ns
SCLK to SLE disable time, readback
ns
TxRxCLK negative edge to SLE
ns
TxRxDATA to TxRxCLK setup time (Tx mode)
ns
TxRxCLK to TxRxDATA hold time (Tx mode)
μs
TxRxCLK negative edge to SLE
μs
SLE positive edge to positive edge of TxRxCLK (Rx mode)
Rev. 0 | Page 10 of 60
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