ADF7025BCPZ-RL View Datasheet(PDF) - Analog Devices
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Description
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ADF7025BCPZ-RL Datasheet PDF : 44 Pages
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Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at approximately
0.75 times the user’s data rate, using Bits R4_DB [6:15].
Bit Slicer
The received data is recovered by the threshold detecting the
output of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on 0. Therefore, the slicer
threshold level can be fixed at 0, and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander
problems that exist in more traditional FSK demodulators.
Data Synchronizer
An oversampled digital PLL is used to resynchronize the received
bit stream to a local clock. The oversampled clock rate of the
PLL (CDR_CLK) must be set at 32 times the data rate. See the
Register 3—Receiver Clock Register section for a definition of
how to program. The clock recovery PLL can accommodate
frequency errors of up to ±2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB [5:4]
should be set to 01. To achieve best performance, the bandwidth
of the FSK correlator must be optimized for the specific deviation
frequency that is used by the FSK transmitter.
ADF7025
The discriminator BW is controlled in Register 6 by
R6_DB [4:13] and is defined as
Discriminator_BW = DEMOD_CLK/(4 × FDEV)
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section.
FDEV is the deviation from the carrier frequency in FSK
modulation.
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB [6:15] and is given by
Post _ Demod _ BW _ Setting = 210 × 2π × FCUTOFF
DEMOD _ CLK
where FCUTOFF is the target 3 dB bandwidth in Hz of the post-
demodulator filter. This should typically be set to 0.75 times
the data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 11.0592 MHz
DR = 200 kbps
FDEV = 300 kHz
Therefore,
FCUTOFF = 0.75 × 200 × 103 Hz
Post_Demod_BW = 211 × π × 150 × 103 Hz/(11.0592 MHz)
Post_Demod_BW = Round (87.266) = 87
and
Discriminator_BW = (11.0592 MHz )/(4 × 300 × 103) =
9.21 = 9 (rounded to the nearest integer)
Table 6. Register Settings
Setting Name
Register Address
Post_Demod_BW R4_DB [6:15]
Discriminator BW R6_DB [4:13]
Value
0x09
0x58
Rev. A | Page 21 of 44
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