ADIS16265ACCZ(RevPrA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADIS16265ACCZ Datasheet PDF : 19 Pages
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Preliminary Technical Data
Flash Memory Endurance
The ENDURANCE register maintains a running count of writes
to the flash memory. It provides up to 32,768 counts. Note that
if this count is exceeded, the register wraps around, and goes
back to zero, before beginning to increment again.
Table 30. ENDURANCE Register Definition
Address
Default
Format
0x01, 0x00
N/A
Binary
Access
Read-only
Alarms
The ADIS16260/ADIS16265 provide two independent alarm
options for event detection. Event detections occur when output
register data meets the configured conditions. Configuration
options are:
• All output data registers are available for monitoring as the
source data.
• The source data can be filtered or unfiltered.
• Comparisons can be static or dynamic (rate of change).
• The threshold levels and times are configurable.
• Comparison can be greater than or less than.
The ALM_MAG1 register and the ALM_MAG2 register both
establish the threshold level for detecting events. They take on the
format of the source data and provide a bit for establishing the
greater than/less than comparison direction. When making
dynamic comparisons, the ALM_SMPL1 register and the
ALM_SMPL2 register establish the number of averages taken for
the source data as a reference for comparison. In this configuration,
each subsequent source data sample is subtracted from the previous
one, establishing an instantaneous delta. The ALM_CTRL register
controls the source data selection, static/dynamic selection, filtering
selection, and digital I/O usage for the alarms.
The rate of change calculation is
YC
=
1
N DS
N DS
∑ y(n + 1) − y(n)
n =1
Rate of change alarm ⇒ is YC > or < M C ?
where:
NDS is the number of samples in ALM_SMPL1/2.
y(n) is the sampled output data.
MC is the magnitude for comparison in ALM_MAG1/2.
YC is the factor to be compared with MC.
> or < is determined by the MSB in ALM_MAG1/2.
ADIS16260/ADIS16265
Table 31. ALM_MAG1 Register Definition
Address
Default
Format
0x21, 0x20
0x0000
N/A
Access
R/W
Table 32. ALM_MAG1 Bit Descriptions
Bit
Description
15
Comparison polarity: 1 = greater than, 0 = less than
14
Not used
13:0 Data bits: format matches source data format
Table 33. ALM_SMPL1 Register Definition
Address
Default
Format
0x25, 0x24
0x0000
Binary
Access
R/W
Table 34. ALM_SMPL1 Bit Descriptions
Bit
Description
15:8 Not used
7:0
Data bits
Table 35. ALM_MAG2 Register Definition
Address
Default
Format
0x23, 0x22
0x0000
N/A
Access
R/W
Table 36. ALM_MAG2 Bit Descriptions
Bit Description
15 Comparison polarity
1 = greater than
0 = less than
14 Not used
13:0 Data bits: format matches source data format
Table 37. ALM_SMPL2 Register Definition
Address
Default
Format
0x27, 0x26
0x0000
Binary
Access
R/W
Table 38. ALM_SMPL2 Bit Designations
Bit
Description
15:8 Not used
7:0
Data bits
Table 39. ALM_CTRL Register Definition
Address
Default
Format
0x29, 0x28
0x0000
N/A
Access
R/W
Rev. PrA | Page 17 of 19
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