ADM1168 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADM1168 Datasheet PDF : 27 Pages
| |||
ADM1168
If none of the states are set as fault record trigger states, then the
black box is considered disabled, and read/write access is allowed
without having to halt the black box fault recorder.
SERIAL BUS INTERFACE
The ADM1168 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1168 to download from its EEPROM.
Therefore, access to the ADM1168 is restricted until the download
is complete.
Identifying the ADM1168 on the SMBus
The ADM1168 has a 7-bit serial bus slave address (see Table 9).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 10001; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1168s to one SMBus.
Table 9. Serial Bus Slave Address
A1 Pin A0 Pin Hex Address
Low
Low
0x88
Low
High
0x8A
High
Low
0x8C
High
High
0x8E
7-Bit Address1
1000100x
1000101x
1000110x
1000111x
1 x = read/write bit. The address is shown only as the first seven MSBs.
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 10 lists these registers
with their values and functions.
Table 10. Identification Register Values and Functions
Name Address Value Function
MANID 0xF4
0x41 Manufacturer ID for Analog Devices
REVID 0xF5
0x10 Silicon revision
MARK1 0xF6
0x00 Software brand
MARK2 0xF7
0x00 Software brand
General SMBus Timing
Figure 25, Figure 26, and Figure 27 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
Data Sheet
The general SMBus protocol operates in the following three steps.
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA,
while the serial clock line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and by holding it low during the high period of this clock pulse.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Step 2
Data is sent over the serial bus in sequences of nine clock pulses,
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
may be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command to
a slave device during a read operation is not possible. Before a read
operation, it may be necessary to perform a write operation to
tell the slave what sort of read operation to expect and the address
from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does not
pull it low. This is known as a no acknowledge. The master then
takes the data line low during the low period before the 10th clock
pulse and then high during the 10th clock pulse to assert a stop
condition.
Rev. B | Page 22 of 27
Share Link: 