ADM483
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RO 1
8 VCC
RE 2 ADM483 7 B
DE 3 TOP VIEW 6 A
DI 4 (Not to Scale) 5 GND
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
RO
2
RE
3
DE
4
DI
5
GND
6
A
7
B
8
VCC
Description
Receiver Output. When enabled, if A > B by 200 mV, then RO = high.
If A < B by 200 mV, then RO = low.
Receiver Output Enable. A low level enables the receiver output, RO.
A high level places it in a high impedance state.
Driver Output Enable. A high level enables the driver differential inputs A and B.
A low level places it in a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high,
while a logic high on DI forces A high and B low.
Ground.
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
5 V Power Supply.
Rev. 0 | Page 6 of 16