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ADP1655 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADP1655 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter1
fSCL
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
tSP
CB
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20 + 0.1 CB2
20 + 0.1 CB
0
Max
Unit
Description
400
kHz
SCL clock frequency
μs
SCL high time
μs
SCL low time
ns
Data setup time
0.9
μs
Data hold time
μs
Setup time for repeated start
μs
Hold time for start/repeated start
μs
Bus free time between a stop and a start condition
μs
Setup time for stop condition
300
ns
Rise time of SCL and SDA
300
ns
Fall time of SCL and SDA
50
ns
Pulse width of suppressed spike
400
pF
Capacitive load for each bus line
1 Guaranteed by design.
2 CB is the total capacitance of one bus line in picofarads.
ADP1655
SDA
tLOW
tR
tSU, DAT
tF
tF
tHD, STA
SCL
S
tHD, DAT
tHIGH
tSU, STA
Sr
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Figure 3. I2C-Compatible Interface Timing Diagram
tSP
tR
tBUF
tSU, STO
P
S
Rev. 0 | Page 5 of 24

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