ADP3159JRU View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3159JRU Datasheet PDF : 16 Pages
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ADP3159/ADP3179
Although a single termination resistor equal to RCOMP would
yield the proper voltage positioning gain, the dc biasing of that
resistor would determine how the regulation band is centered
(i.e., offset). Note that sometimes the specified regulation band
is asymmetrical with respect to the nominal VID voltage. With
the ADP3159, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the
dc biasing, it is simplest to use two resistors to terminate the gm
amplifier output, with the lower resistor (RB) tied to ground and
the upper resistor (RA) to the 12 V supply of the IC. The values
of these resistors can be calculated using:
RA
=
gm
VDIV
× (VOUT (OS )
+ K)
=
12 V
2.2 mmho × (22 mV
+ 4.7 × 10–2 )
= 79.1 kΩ
(26)
where K is a constant determined by internal characteristics of
the ADP3159, peak-to-peak inductor current ripple (IRIPPLE),
and the current sampling resistor (RSENSE). K can be calculated
using Equations 28 and 29. VDIV is the resistor divider supply
voltage (e.g., the recommended 12 V supply) and VOUT(OS) is
the output voltage offset from the nominal VID-programmed
value under no load condition. This offset is given by Equation 30.
The closest 1% value for RA is 78.7 kΩ. This value is then used
to solve for RB:
RB
=
RA × RCOMP
RA – RCOMP
= 78.7 kΩ × 9.2 kΩ
78.7 kΩ – 9.2 kΩ
= 10.4 kΩ
(27)
The nearest 1% value of 10.5 kΩ was chosen for RB.
K
=
I L( RIPPLE
2
)
×
(RSENSE × nI
gm × RTOTAL
)
+
VGNL
gm × RTOTAL
–
VCC
2 × gm ROGM
K
=
3.8
2
A
×
2.2
4 mΩ
mmho
×
×
25
9.1
kΩ
+
1.174
2.2 mmho × 9.1 kΩ
−
12 V
2 × 2.2 mmho × 130 kΩ
(28)
= 4.7 × 10–2
VGNL
= VGNLO
+
I L( RIPPLE ) × RSENSE
2
× nI
−
VIN
− VVID
L
× tD
× RSENSE
×
nI
VGNL
= 1V
+
3.8
A × 4 mΩ × 25
2
−
5V –
1.5
1.7 V
µH
×
75
ns
×
4
mΩ
×
25
= 1.174 V
(29)
( ) VOUT (OS ) = VOUT ( MAX ) − VVID
−
RE ( MAX )
× I L( RIPPLE )
2
− VVID
× kVID
VOUT (OS )
=
40 mV
−
5 mΩ
× 3.8
2
A
− 1.7V
× 5 × 10–3
=
22
mV
(30)
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
COC
=
COUT × ESR
RTOTAL
=
5 mF × 4.8 mΩ
9.1 kΩ
=
2.6 nF
(31)
The closest standard value for COC is 2.7 nF
Trade-Offs Between DC Load Regulation and AC Load
Regulation
Casual observation of the circuit operation—e.g., with a voltmeter
—would make it appear that the dc load regulation appears to
be rather poor compared to a conventional regulator (see Figure
4). This would be especially noticeable under very light or very
heavy loads where the voltage is “positioned” near one of the
extremes of the regulation window rather than near the nominal
center value. It must be noted and understood that this low gain
characteristic (i.e., loose dc load regulation) is inherently required
to allow improved transient containment (i.e., to achieve tighter
ac load regulation). That is, the dc load regulation is intentionally
sacrificed (but kept within specification) in order to minimize
the number of capacitors required to contain the load transients
produced by the CPU.
3.3V
ADP3159 /A DP3179
1F
VLR2
2.5V, 2.2A
RS
250m⍀
100F
1k⍀
68pF
10k⍀
LRDRV1
LRFB1
2.5V
Figure 6. Adding Overcurrent Protection to the
Linear Regulator
Linear Regulators
The two linear regulators provide a low cost, convenient and
versatile solution for generating additional supply rails. The
maximum output load current is determined by the size and
thermal impedance of the external N-channel power MOSFET
that is placed in series with the supply. The output voltage is
sensed at the LRFB pin and compared to an internal reference
voltage in a negative feedback loop which keeps the output voltage
in regulation. If the load is reduced or increased, the MOSFET
drive will also be reduced or increased by the controller IC to
provide a well-regulated ± 2.5% accurate output voltage.
The LRFB threshholds of the ADP3159 are internally set at
2.5 V(LRFB1) and 1.8 V(LRFB2), while the LRFB pins of the
ADP3179 are compared to an internal 1 V reference. This allows
the use of an external resistor divider network to program the
linear regulator output voltage. The correct resistor values for
setting the output voltage of the linear regulators in the
ADP3179 can be determined using:
VOUT(LR)
= VLRFB
×
RU + RL
RL
(32)
Assuming that RL =10 kΩ, VOUT(LR) = 1.2 V and rearranging
equation 32 to solve for RU yields:
( ) RU
=
10 kΩ ×
VOUT(LR) − VLRFB
VLRFB
(33)
10 kΩ × (1.2V − 1V )
RU =
1V
= 2 kΩ
REV. A
–11–
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