ADP3153 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3153 Datasheet PDF : 12 Pages
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ADP3153
The compensating capacitance is determined from the equality
of the pole frequency of the error amplifier gain and the zero
frequency of the impedance of the output capacitor.
CCOMP
=
RE COUT
RCOMP
=
5 m ×16.2 mF
31kΩ
=
2.6 nF
In the application circuit we tested, we found that the compen-
sation scheme shown in Figure 2 gave the optimal response to
meet the Pentium II dc/dc static and transient specifications
with sufficient margins including the ADP3153’s initial error
tolerance, the PCB layout trace resistances, and the external
component parasitics. If we increase the load resistance to the
COMP pin, the static regulation will improve. The load transient
response, however, will get worse. In Figure 2, if we decrease the
R1 = 150 kΩ resistor vs. the R2 = 39 kΩ resistor, the regulation
band will shift positive in relation to the 2.8 V. If we increase
the R1 resistor, the regulation band will shift negative. It may be
necessary to adjust these resistor values to obtain the best static
and dynamic regulation compliance depending on the output
capacitor ESR and the parasitic trace resistances of the PCB
layout. A detailed design procedure and published conference
papers on the optimal compensation are available on ADI’s
website (http://www.analog.com).
ADP3153 Linear Regulator
The ADP3153 linear regulator provides a low cost, convenient,
and versatile solution for generating an additional power supply
rail that can be programmed between 1.2 V–5 V. The maximum
output load current is determined by the size and thermal imped-
ance of an external N-channel power MOSFET that is placed in
series with the 5 V supply and controlled by the ADP3153. The
output voltage, VO2 in Figure 14, is sensed at the FB pin of the
ADP3153 and compared to an internal 1.2 V reference in a
negative feedback loop which keeps the output voltage in regula-
tion. Thus, if the load is being reduced or increased, the FET
drive will also be reduced or increased by the ADP3153 to pro-
vide a well regulated ± 1% accurate output voltage. This accu-
racy is maintained even if the load changes at the very high rate
typical of CPU-type loads. The output voltage is programmed
by adjusting the value of the external resistor RPROG shown in
Figure 14.
Features
• Typical Efficiency: 66% at 3.3 V Output Voltage
• Tight DC Regulation Due to 1% Reference and High Gain
• Output Voltage Stays Within Specified Limits at Load Cur-
rent Step with 30 A/µs Slope
• Fast Response to Input Voltage or Load Current Transients
The design in Figure 14 is for an output voltage, VO2 of 3.3 V
with a maximum load current of 0.5 A. Additionally, overcurrent
protection is provided by the addition of an external NPN tran-
sistor and an external resistor RS2. The design specifications and
procedure is given below.
Linear Regulator Design Specifications
Maximum Ambient Temperature . . . . . . . . . . . TAMB = 50°C
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN = 5 V
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VO2 = 3.3 V
Maximum Output Current . . . . . . . . . . . . . . . IO2MAX = 0.5 A
Maximum Output Load Transient Allowed . . VTR2 = 0.036 V
Chosen FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRX3803
Junction-to-Ambient Thermal Impedance (FET)*
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
*Uses 1 inch square PCB cu-foil as heatsink
The output voltage may be programmed by the resistor RPROG
as follows:
RPROG
=
VO2
1.2
–1
×
20
kΩ
=
3.3
1.2
–1
× 20
kΩ
=
35 kΩ
The current sense resistor may be calculated as follows:
RS2
=
0.6
IO2 MAX
= 0.6 =1.2 Ω
0.5
The power rating is:
( )2
PS2 = RS2 × IO2MAX ×1.1 = 0.36W
Use a 0.5 Ω resistor.
The maximum FET junction temperature at shorted output is:
TFETMAX = TAMB + θJA ×VIN × IO2MAX ×1.1=
50 + 40 × 5 × 0.5 ×1.1=160°C
which is within the maximum allowed by the FET's data sheet.
The maximum FET junction temperature at nominal output is:
( ) TFETMAX = TAMB + θJA × VIN –VO2 × IO2MAX =
( ) 50 + 40 × 5– 3.3 × 0.5 = 84°C
The output filter capacitor maximum allowed ESR is:
ESR ~ VTR2/IOMAX = 0.036/0.5 = 0.072 Ω.
This requirement is met using a 1000 µF/10 V LXV series ca-
pacitor from United Chemicon. For applications requiring
higher output current, a heatsink and/or a larger MOSFET
should be used to reduce the MOSFET’s junction to ambient
thermal impedance.
VO2 = 3.3V
IO2 = 0.5A
VIN = +5V
RS2
1.1⍀
IRX3803
2k⍀
470pF
ADP3153
VLDO
FB
2N2222
1000F/10V
RPROG
35k⍀
20k⍀
Figure 14. Linear Regulator with Overcurrent Protection
–10–
REV. 0
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