ADP7105ARDZ(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP7105ARDZ Datasheet PDF : 28 Pages
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Data Sheet
20 V, 500 mA, Low Noise LDO Regulator
with Soft Start
ADP7105
FEATURES
Input voltage range: 3.3 V to 20 V
Maximum output current: 500 mA
Low noise: 15 µV rms for fixed output versions
PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V
Reverse current protection
Low dropout voltage: 350 mV at 500 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature: −2% to +1%
Low quiescent current: 900 μA at VIN = 10 V, IOUT = 500 mA
Low shutdown current: <50 µA at VIN = 12 V, stable with small
1 µF ceramic output capacitor
3 fixed output voltage options: 1.8, 3.3 V and 5 V
Adjustable output from 1.22 V to 19 V
Programmable soft start for inrush current control
Foldback current-limit and thermal overload protection
User programmable precision UVLO/enable
Power-good indicator
8-lead LFCSP and 8-lead SOIC packages
APPLICATIONS
Regulation of noise sensitive applications: ADC and DAC
circuits, precision amplifiers, high frequency oscillators,
clocks, and PLLs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7105 is a CMOS, low dropout (LDO)linear regulator
that operates from 3.3 V to 20 V and provides up to 500 mA of
output current. This high input voltage LDO is ideal for regula-
tion of high performance analog and mixed-signal circuits
operating from 1.22 V to 19 V rails. Using an advanced proprie-
tary architecture, the ADP7105 provides high power supply
rejection and low noise, and achieves excellent line and load
transient response with only a small 1 µF ceramic output
capacitor.
The ADP7105 is available in three fixed output voltage options
and an adjustable version that allows output voltages ranging
from 1.22 V to 19 V via an external feedback divider. The
ADP7105 allows an external soft start capacitor to be connected
to program the startup.
TYPICAL APPLICATION CIRCUITS
VIN = 8V
CIN +
1µF
ON
OFF
100kΩ
100kΩ
VIN VOUT
SENSE
EN/
UVLO
PG
GND SS
+ COUT
1µF
VOUT = 5V
100kΩ
PG
CSS
Figure 1. ADP7105 with Fixed Output Voltage, 5 V
VIN = 8V
CIN +
1µF
ON
OFF
100kΩ
100kΩ
VIN VOUT
ADJ
EN/
UVLO
PG
GND SS
40.2kΩ
+
VOUT
COUT
=
5V
1µF
13kΩ
100kΩ
PG
CSS
Figure 2. ADP7105 with Adjustable Output Voltage, 5 V
Note that throughout this data sheet, the sense function
(SENSE) of the SENSE/ADJ pin applies to fixed output voltage
models only, whereas the adjust input function (ADJ) applies to
adjustable output voltage models only. For example, Figure 1
shows the sense function, and Figure 2 shows the adjust input
function.
The ADP7105 output noise voltage is 15 μV rms and is inde-
pendent of the output voltage. A digital power-good output
allows power system monitors to check the health of the output
voltage. A user programmable precision undervoltage lockout
function facilitates sequencing of multiple power supplies.
The ADP7105 is available in 8-lead, 3 mm × 3 mm LFCSP
and 8-lead SOIC packages. The LFCSP offers a very compact
solution and provides excellent thermal performance for
applications that require up to 500 mA of output current in a
small, low profile footprint.
Rev. 0
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