ADSP-21161NKCA-100(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-21161NKCA-100 Datasheet PDF : 60 Pages
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ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin
BMS
Type
I/O/T
CLKIN
I
XTAL
O
CLK_CFG1-0 I
CLKDBL
I
CLKOUT
O/T
RESET
I/A
Function
Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins (see Table 4). This input is a system configuration selection that should be
hardwired. For Host and PROM boot, DMA channel 10 (EPB0) is used. For Link boot and
SPI boot, DMA channel 8 is used.
Three-state only in EPROM boot mode (when BMS is an output).
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input.
It configures the ADSP-21161N to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-21161N to use the external clock source such as an external clock
oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The
instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-
up via the CLK_CFG1–0 pins. CLKIN may not be halted, changed, or operated below the
specified frequency.
Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-
21161N’s internal clock oscillator or to disable it to use an external clock source. See CLKIN.
Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal
to n × PLLICLK where n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs.
These pins can also be used in combination with the CLKDBL pin to generate additional
core clock rates of 6 × CLKIN and 8 × CLKIN (see the Clock Rate Ratios table in the
CLKDBL description).
Crystal Double Mode Enable. This pin is used to enable the 2× clock double circuitry,
where CLKOUT can be configured as either 1× or 2× the rate of CLKIN. This CLKIN
double circuit is primarily intended to be used for an external crystal in conjunction with
the internal clock generator and the XTAL pin. The internal clock generator when used in
conjunction with the XTAL pin and an external crystal is designed to support up to a
maximum of 25 MHz external crystal frequency. CLKDBL can be used in XTAL mode to
generate a 50 MHz input into the PLL. The 2× clock mode is enabled (during RESET low)
by tying CLKDBL to GND, otherwise it is connected to VDDEXT for 1× clock mode. For
example, this enables the use of a 25 MHz crystal to enable 100 MHz core clock rates and
a 50 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.
This pin can also be used to generate different clock rate ratios for external clock oscillators
as well. The possible clock rate ratio options (up to 100 MHz) for either CLKIN (external
clock oscillator) or XTAL (crystal input) are shown in Table 3 on Page 17. An 8:1 ratio
enables the use of a 12.5 MHz crystal to generate a 100 MHz core (instruction clock) rate
and a 25 MHz CLKOUT (external port) clock rate. See also Figure 10 on Page 20.
Note: When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz.
For all other external clock sources, the maximum CLKIN frequency is 50 MHz.
Local Clock Out. CLKOUT is 1× or 2× and is driven at either 1× or 2× the frequency of
CLKIN frequency by the current bus master. The frequency is determined by the CLKDBL
pin. This output is three-stated when the ADSP-21161N is not the bus master or when the
host controls the bus (HBG asserted). A keeper latch on the DSP’s CLKOUT pin maintains
the output at the level it was last driven. This latch is only enabled on the ADSP-21161N
with ID2–0=00x.
If CLKDBL enabled, CLKOUT=2 × CLKIN
If CLKDBL disabled, CLKOUT=1 × CLKIN
Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 × CLKIN or
2 × CLKIN.
Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.
Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the
program memory location specified by the hardware reset vector address. The RESET input
must be asserted (low) at power-up.
–16–
REV. A
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