ADSP-21267 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21267

SHARC® Processor

Analog Devices 

ADSP-21267

PRELIMINARY TECHNICAL DATA

LONG WORD

ADDRESSING

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0.5 Mbit)

0x0004 0000 - 0x0004 1FFF

RESERVED

0x0004 2000 - 0x0005 7FFF

BLOCK 0 ROM (1.5 mbit)

0x0005 8000 - 0x0002 FFFF

RESERVED

0x0005 3000 - 0x0005 FFFF

BLOCK 1 SRAM (0.5 Mbit)

0x0006 0000 - 0x0006 1FFF

RESERVED

0x0006 2000 - 0x0007 7FFF

BLOCK 1 ROM (1.5 mbit)

0x0007 8000 - 0x0007 DFFF

RESERVED

0x0007 E000 - 0x0007 FFFF

INTERNAL MEMORY

SPACE

NORMAL WORD

ADDRESSING

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0.5 Mbit)

0x0008 0000 - 0x0008 3FFF

RESERVED

0x0008 4000 - 0x000A FFFF

BLOCK 0 ROM (1.5 mbit)

0x000B 0000 - 0x000B BFFF

RESERVED

0x000B C000 - 0x000B FFFF

BLOCK 1 SRAM (0.5 Mbit)

0x000C 0000 - 0x000C 3FFF

RESERVED

0x000C 4000 - 0x000E FFFF

BLOCK 1 ROM (1.5 mbit)

0x000F 0000 - 0x000F BFFF

RESERVED

0x000F C000 - 0x000F FFFF

SHORT WORD

ADDRESSING

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0.5 Mbit)

0x0010 0000 - 0x0010 7FFF

RESERVED

0x0010 8000 - 0x0015 FFFF

BLOCK 0 ROM (1.5 mbit)

0x0016 0000 - 0x0017 7FFF

RESERVED

0x0017 8FFF - 0x0017 FFFF

BLOCK 1 SRAM (0.5 Mbit)

0x0018 0000 - 0x0018 7FFF

RESERVED

0x0018 8000 - 0x001D FFFF

BLOCK 1 ROM (1.5 mbit)

0x001E 0000 - 0x001F 7FFF

RESERVED

0x000

EXTERNAL MEMORY

SPACE

RESERVED

0x0020 0000 - 0x00FF FFFF

EXTERNAL DMA

ADDRESS SPACE1

0x0100 0000 - 0x02FF FFFF

RESERVED

0x0300 0000 - 0x3FFF FFFF

1EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE

BY THE CORE. DMA MUST BE USED TO READ OR WRITE

TO THIS MEMORY USING THE SPI OR PARALLEL PORT.

2BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE

(0x000A 0000 - 0x000A AAAA).

3BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE

(0x000E 0000 - 0x000E AAA).

Figure 3. ADSP-21267 Memory Map

• I2S mode

• Left-justified sample pair mode

Left-justified Sample Pair Mode is a mode where in each Frame

Sync cycle two samples of data are transmitted/received — one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the Left-justified Sample Pair

and I2S protocols (I2S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four Left-justified Sample Pair or I2S channels (using two stereo

devices) per serial port, with a maximum of up to 16 audio

channels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the Left-justified Sample Pair and I2S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional µ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard syn-

chronous serial link, enabling the ADSP-21267 SPI-compatible

port to communicate with other SPI-compatible devices. SPI is

an interface consisting of two data pins, one device select pin,

and one clock pin. It is a full-duplex synchronous serial inter-

face, supporting both master and slave modes. The SPI port can

operate in a multi-master environment by interfacing with up to

four other SPI-compatible devices, either acting as a master or

Rev. PrA | Page 6 of 44 | January 2004

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