ADSP-21365(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-21365 Datasheet PDF : 52 Pages
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 4. Pin Descriptions (Continued)
State During and
Pin
Type
After Reset
Description
RSTOUT/CLKOUT O
Output only
Local Clock Out/Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin. The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.
The default is reset out.
RESET
TCK
I/A
Input only
Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
I
Input only3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
TMS
I/S
Three-state with Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
(pu)
pull-up enabled internal pull-up resistor.
TDI
I/S
Three-state with Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
(pu)
pull-up enabled 22.5 kΩ internal pull-up resistor.
TDO
O
Three-state4
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
(pu)
pull-up enabled after power-up or held low for proper operation of the ADSP-2136x. TRST has a
22.5 kΩ internal pull-up resistor.
EMU
O (O/D) Three-state with Emulation Status. Must be connected to the processor’s JTAG emulators target board
(pu)
pull-up enabled connector only. EMU has a 22.5 kΩ internal pull-up resistor.
VDDINT
P
Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and
1.0 V dc for the Y and W grade models, and supplies the processor’s core (13 pins).
VDDEXT
P
I/O Power Supply. Nominally +3.3 V dc (6 pins).
AVDD
P
Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and
1.0 V dc for the Y and W Grade models, and supplies the processor’s internal PLL (clock
generator). This pin has the same specifications as VDDINT, except that added filtering
circuitry is required. For more information, see Power Supplies on Page 9.
AVSS
G
GND
G
Analog Power Supply Return.
Power Supply Return. (54 pins)
1 RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2 Output only is a three-state driver with its output path always enabled.
3 Input only is a three-state driver with both output path and pull-up disabled.
4 Three-state is a three-state driver with pull-up disabled.
Rev. A | Page 14 of 52 | December 2006
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