ADSP-21990BST View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21990BST

Mixed-Signal DSP Controller

Analog Devices 

ADSP-21990

peripheral interrupt controller is used to assign the various

peripheral interrupts to the 12 user assignable interrupts of the

DSP core.

Table 2. Interrupt Priorities/Addresses

Interrupt

Emulator (NMI)

—Highest Priority

Reset (NMI)

Power Down (NMI)

Loop and PC Stack

Emulation Kernel

User Assigned Interrupt

(USR0)

User Assigned Interrupt

(USR1)

User Assigned Interrupt

(USR2)

User Assigned Interrupt

(USR3)

User Assigned Interrupt

(USR4)

User Assigned Interrupt

(USR5)

User Assigned Interrupt

(USR6)

User Assigned Interrupt

(USR7)

User Assigned Interrupt

(USR8)

User Assigned Interrupt

(USR9)

User Assigned Interrupt

(USR10)

User Assigned Interrupt

(USR11)

—Lowest Priority

IMASK/

IRPTL

NA

Vector Address

NA

0

0x00 0000

1

0x00 0020

2

0x00 0040

3

0x00 0060

4

0x00 0080

5

0x00 00A0

6

0x00 00C0

7

0x00 00E0

8

0x00 0100

9

0x00 0120

10

0x00 0140

11

0x00 0160

12

0x00 0180

13

0x00 01A0

14

0x00 01C0

15

0x00 01E0

There is no assigned priority for the peripheral interrupts after

reset. To assign the peripheral interrupts a different priority,

applications write the new priority to their corresponding con-

trol bits (determined by their ID) in the interrupt priority

control register.

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The emulation, power down, and reset interrupts are

nonmaskable with the IMASK register, but software can use the

DIS INT instruction to mask the power-down interrupt.

The interrupt control (ICNTL) register controls interrupt nest-

ing and enables or disables interrupts globally.

The IRPTL register is used to force and clear interrupts. On-

chip stacks preserve the processor status and are automatically

maintained during interrupt handling. To support interrupt,

loop, and subroutine nesting, the PC stack is 33 levels deep, the

loop stack is eight levels deep, and the status stack is 16 levels

deep. To prevent stack overflow, the PC stack can generate a

stack level interrupt if the PC stack falls below three locations

full or rises above 28 locations full.

The following instructions globally enable or disable interrupt

servicing, regardless of the state of IMASK:

• Ena Int.

• Dis Int.

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG and

computational registers exist. Switching between the primary

and secondary registers lets programs quickly service interrupts,

while preserving the state of the DSP.

PERIPHERAL INTERRUPT CONTROLLER

The peripheral interrupt controller is a dedicated peripheral

unit of the ADSP-21990 (accessed via I/O mapped registers).

The peripheral interrupt controller manages the connection of

up to 32 peripheral interrupt requests to the DSP core.

For each peripheral interrupt source, there is a unique 4-bit

code that allows the user to assign the particular peripheral

interrupt to any one of the 12 user assignable interrupts of the

embedded ADSP-2199x core. Therefore, the peripheral inter-

rupt controller of the ADSP-21990 contains eight, 16-bit

interrupt priority registers (Interrupt Priority Register 0 (IPR0)

to Interrupt Priority Register 7 (IPR7)).

Each interrupt priority register contains four 4-bit codes; one

specifically assigned to each peripheral interrupt. The user may

write a value between 0x0 and 0xB to each 4-bit location in

order to effectively connect the particular interrupt source to

the corresponding user assignable interrupt of the

ADSP-2199x core.

Writing a value of 0x0 connects the peripheral interrupt to the

USR0 user assignable interrupt of the ADSP-2199x core while

writing a value of 0xB connects the peripheral interrupt to the

USR11 user assignable interrupt. The core interrupt USR0 is the

highest priority user interrupt, while USR11 is the lowest prior-

ity. Writing a value between 0xC and 0xF effectively disables the

peripheral interrupt by not connecting it to any ADSP-2199x

core interrupt input. The user may assign more than one

peripheral interrupt to any given ADSP-2199x core interrupt. In

that case, the burden is on the user software in the interrupt vec-

tor table to determine the exact interrupt source through

reading status bits.

This scheme permits the user to assign the number of specific

interrupts that are unique to their application to the interrupt

scheme of the ADSP-2199x core. The user can then use the

existing interrupt priority control scheme to dynamically con-

trol the priorities of the 12 core interrupts.

Rev. A | Page 11 of 50 | August 2007

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