ADSP-21992YST(RevPrA) View Datasheet(PDF) - Analog Devices
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ADSP-21992YST Datasheet PDF : 48 Pages
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PRELIMINARY TECHNICAL DATA
ADSP-21992
For current information contact Analog Devices at (781) 937-1799
August 2002
input to any unit on the next cycle. For conditional or mul-
tifunction instructions, there are restrictions on which data
registers may provide inputs or receive results from each
computational unit. For more information, see the
ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruc-
tion execution. The sequencer supports conditional jumps,
subroutine calls, and low interrupt overhead. With internal
loop counters and loop stacks, the ADSP-21992 executes
looped code with zero overhead; no explicit jump instruc-
tions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to
access data (indirect addressing), it is pre- or post-modified
by the value of one of four possible modify registers. A length
value and base address may be associated with each pointer
to implement automatic modulo addressing for circular
buffers. Page registers in the DAGs allow circular addressing
within 64K word boundaries of each of the 256 memory
pages, but these buffers may not cross page boundaries.
Secondary registers duplicate all the primary registers in the
DAGs; switching between primary and secondary registers
provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Direct Memory Access Address Bus
• Direct Memory Access Data Bus
The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded off
chip, and the two data buses (PMD and DMD) share a
single external data bus. Boot memory space and I/O
memory space also share the external buses.
Program memory can store both instructions and data, per-
mitting the ADSP-21992 to fetch two operands in a single
cycle, one from program memory and one from data
memory. The DSP’s dual memory buses also let the
embedded ADSP-219x core fetch an operand from data
memory and the next instruction from program memory in
a single cycle.
Memory Architecture
The ADSP-21992 provides 48K words of on chip SRAM
memory. This memory is divided into two blocks; a 32K x
24-bit (block 0) and a 16K x 16-bit (block 1). In addition,
the ADSP-21992 provides a 4k x 24-bit block of program
memory boot ROM (that is reserved by ADI for boot load
routines). The memory map of the ADSP-21992 is illus-
trated in Figure 2.
As shown in Figure 2, the two internal memory RAM blocks
reside in memory page 0. The entire DSP memory map
consists of 256 pages (pages 0 to 255), and each page is 64
kWords long. External memory space consists of four
memory banks (banks 0-3) and supports a wide variety of
memory devices. Each bank is selectable using unique
memory select lines (MS3 - MS0) and has configurable page
boundaries, wait states, and wait state modes. The 4K words
of on chip boot ROM populates the top of page 255, while
the remaining 254 pages are addressable off chip. I/O
memory pages differ from external memory in that they are
1K word long, and the external I/O pages have their own
select pin (IOMS). Pages 0-31 of I/O memory space reside
on chip and contain the configuration registers for the
peripherals. Both the ADSP_219x core and DMA capable
peripherals can access the DSP’s entire memory map.
0x000000
BLOCK 0: 32K X 24-BIT RAM
0x00 7FFF
0x00 8000
0x00 BFFF
0x00 C000
0x00 FFFF
0x01 0000
BLOCK 1: 16K X 16-BIT RAM
RESERVED (16K)
EXTERNAL MEMORY
(4M - 64K)
0x40 0000
EXTERNAL MEMORY
0x80 0000
EXTERNAL MEMORY
0xC0 0000
0xFF 0000
0xFF 0FFF
0xFF 1000
0xFF FFFF
EXTERNAL MEMORY
(4M - 64K)
BLOCK 2: 4K X 24-BIT
PM ROM
UNUSED ON-CHIP
MEMORY (60K)
PAGE 0 (64K) ON-CHIP
(0 WAIT STATE)
PAGES 1 TO 63
BANK 0 (OFF-CHIP)
MS0
PAGES 64 TO 127
BANK 1 (OFF-CHIP)
MS1
PAGES 128 TO 191
MS2
BANK 2 (OFF-CHIP)
PAGES 192 TO 254
BANK 0 (OFF-CHIP) MS3
PAGE 255
(ON-CHIP
Figure 2. ADSP-21992 DSP Core Memory Map at Reset
NOTE: The physical external memory addresses are limited
by 20 address lines, and are determined by the external data
width and packing of the external memory space. The
Strobe signals (MS3 - 0) can be programmed to allow the
user to change starting page addresses at run time.
Internal (On chip) Memory
The ADSP-21992’s unified program and data memory
space consists of 16M locations that are accessible through
two 24-bit address buses, the PMA and DMA buses. The
4 This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing
REV. PrA
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