ADSP-BF533WYBCZ-4A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF533WYBCZ-4A

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF531/ADSP-BF532/ADSP-BF533

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor

Peripherals ....................................................... 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 4

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 8

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Port ....................... 10

UART Port ........................................................ 10

General-Purpose I/O Port F ................................... 10

Parallel Peripheral Interface ................................... 11

Dynamic Power Management ................................ 11

Voltage Regulation .............................................. 13

Clock Signals ..................................................... 13

Booting Modes ................................................... 14

Instruction Set Description ................................... 15

Development Tools ............................................. 15

Designing an Emulator-Compatible Processor Board .. 16

Related Documents ............................................. 17

Pin Descriptions .................................................... 18

Specifications ........................................................ 21

Operating Conditions .......................................... 21

Electrical Characteristics ....................................... 22

Absolute Maximum Ratings .................................. 23

Package Information ........................................... 23

ESD Sensitivity ................................................... 23

Timing Specifications .......................................... 24

Clock and Reset Timing .................................... 25

Asynchronous Memory Read Cycle Timing ........... 26

Asynchronous Memory Write Cycle Timing .......... 27

SDRAM Interface Timing .................................. 28

External Port Bus Request and Grant Cycle Timing .. 29

Parallel Peripheral Interface Timing ..................... 30

Serial Ports ..................................................... 34

Serial Peripheral Interface (SPI) Port

—Master Timing .......................................... 37

Serial Peripheral Interface (SPI) Port

—Slave Timing ............................................. 38

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 39

General-Purpose I/O Port F Pin Cycle Timing ......... 40

Timer Cycle Timing .......................................... 41

JTAG Test and Emulation Port Timing .................. 42

Output Drive Currents ......................................... 43

Power Dissipation ............................................... 45

Test Conditions .................................................. 45

Environmental Conditions .................................... 48

160-Ball BGA Ball Assignment .................................. 49

169-Ball PBGA ball assignment .................................. 52

176-Lead LQFP Pinout ............................................ 55

Outline Dimensions ................................................ 57

Surface Mount Design .......................................... 58

Ordering Guide ..................................................... 59

REVISION HISTORY

7/07—Revision E: Changed from Rev. D to Rev. E

Combined ADSP-BF531/532 Rev D and ADSP-BF533 Rev D

Data sheets into this Revision E .................................. 1

Changed Features .................................................... 1

Reformatted Processor Comparison ............................. 3

Rewrote General-Purpose I/O Port F ........................... 10

Rewrote Parallel Peripheral Interface ........................... 11

Rewrote Dynamic Power Management ........................ 11

Rewrote Voltage Regulation ...................................... 13

Rewrote Clock Signals ............................................. 13

Rewrote Booting Modes ........................................... 14

Rewrote EZ-KIT Lite Evaluation Board ........................ 16

Reformatted Pin Descriptions .................................... 18

Changed Operating Conditions ................................. 21

Changed Electrical Characteristics .............................. 22

Reformatted Timing Specifications ............................. 24

Added Figures to Parallel Peripheral Interface Timing ..... 30

Changed Serial Ports ............................................... 34

Changed Ordering Guide ......................................... 59

8/06—Revision D: Changed from Rev. C to Rev. D

Rev. E | Page 2 of 60 | July 2007

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