ADSP-BF532WBSTZ-4A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF532WBSTZ-4A

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF531/ADSP-BF532/ADSP-BF533

ADDRESS ARITHMETIC UNIT

DA1 32

DA0 32

I3 L3 B3

M3

I2 L2 B2

M2

I1 L1 B1

M1

I0 L0 B0

M0

32

RAB

DAG1

DAG0

SP

FP

P5

P4

P3

P2

P1

P0

32

PREG

SD

32

LD1

32

LD0

32

32

32

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

16

8

8

BARREL

SHIFTER

40

ASTAT

16

8

8

40

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

A0

40 40

A1

32

32

DATA ARITHMETIC UNIT

CONTROL

UNIT

Figure 2. Blackfin Processor Core

The second on-chip memory block is the L1 data memory, con­

sisting of one or two banks of up to 32K bytes. The memory

banks are configurable, offering both cache and SRAM func­

tionality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the external bus interface unit

(EBIU). This 16-bit interface provides a glueless connection to a

bank of synchronous DRAM (SDRAM) as well as up to four

banks of asynchronous memory devices including flash,

EPROM, ROM, SRAM, and memory mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM. The SDRAM con­

troller allows one row to be open for each internal SDRAM

bank, for up to four internal SDRAM banks, improving overall

system performance.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully popu­

lated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space.

On-chip I/O devices have their control registers mapped into

memory mapped registers (MMRs) at addresses near the top of

the 4G byte address space. These are separated into two smaller

blocks, one containing the control MMRs for all core functions,

and the other containing the registers needed for setup and con­

trol of the on-chip peripherals outside of the core. The MMRs

are accessible only in supervisor mode and appear as reserved

space to on-chip peripherals.

Booting

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor con­

tains a small boot kernel, which configures the appropriate

peripheral for booting. If the ADSP-BF531/ADSP-BF532/

ADSP-BF533 processor is configured to boot from boot ROM

memory space, the processor starts executing from the on-chip

boot ROM. For more information, see Booting Modes on

Page 14.

Rev. E | Page 5 of 60 | July 2007

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