ADT7460(2013) View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

ADT7460
(Rev.:2013)

Remote Thermal Monitor and Fan Controller

ON Semiconductor 

ADT7460

Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)

Parameter (Note 1)

Test Conditions/Comments

Typ

Min (Note 2) Max

Unit

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Hysteresis

DIGITAL INPUT LOGIC LEVELS (THERM)

−

0.5

−

Vp−p

Input High Voltage, VIH

Input Low Voltage, VIL

DIGITAL INPUT CURRENT

Input High Current, IIH

Input Low Current, IIL

Input Capacitance, CIN

SERIAL BUS TIMING (Note 4)

VIN = VCC

VIN = 0

1.7

−

−

V

−

−

0.8

V

−1.0

−

−

mA

−

−

+1.0

mA

−

5.0

−

pF

Clock Frequency, fSCLK

See Figure 2

−

−

400

kHz

Glitch Immunity, tSW

−

−

50

ns

Bus Free Time, tBUF

See Figure 2

1.3

−

−

ms

Start Setup Time, tSU;STA

See Figure 2

0.6

−

−

ms

Start Hold Time, tHD;STA

See Figure 2

0.6

−

−

ms

SCL Low Time, tLOW

See Figure 2

1.3

−

−

ms

SCL High Time, tHIGH

See Figure 2

0.6

−

−

ms

SCL, SDA Rise Time, tR

See Figure 2

−

−

300

ns

SCL, SDA Fall Time, tF

See Figure 2

−

−

300

ms

Data Setup Time, tSU;DAT

See Figure 2

100

−

−

ns

Detect Clock Low Timeout, tTIMEOUT

Can be Optionally Disabled

15

−

35

ms

1. All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to VMAX even when

the device is operating below VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a

rising edge.

2. Typicals are at TA = 25°C and represent the most likely parametric norm.

3. The delay is the time between the round robin finishing one set of measurements and starting the next.

4. Guaranteed by design; not production tested

SCL

SDA

tBUF

P

S

t LOW

tR

tHD; STA

tHD; DAT

tF

tHIGH

tSU; DAT

t HD; STA

tSU; STA

S

Figure 2. Serial Bus Timing Diagram

tSU; STO

P

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