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ADT7485AARMZ View Datasheet(PDF) - ON Semiconductor

Part Name
Description
Manufacturer
ADT7485AARMZ Datasheet PDF : 12 Pages
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ADT7485A
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Parameter
Test Conditions/Comments
Min
Typ
Digital I/O (SST Pin)
High Impedance State Leakage, ILEAK
Device powered on SST bus;
VSST = 1.1 V, VCC = 3.3 V
High Impedance State Leakage, ILEAK
Device nonpowered on SST bus;
VSST = 1.1 V, VCC = 0 V
Signal Noise Immunity, VNOISE
Noise glitches from 10 MHz to 100 MHz;
300
width up to 50 ns
SST Timing
Bitwise Period, tBIT
High Level Time for Logic 1, tH1
(Note 2)
High Level Time for Logic 0, tH0
(Note 2)
Time to Assert SST High for Logic 1,
tSU, HIGH
Hold Time, tHOLD (Note 3)
tBIT defined in speed negotiation
See SST Specification Rev 1.0
0.495
0.6 x
tBIT
0.2 x
tBIT
0.75 x
tBIT
0.25 x
tBIT
Stop Time, tSTOP
Time to Respond After a Reset, tRESET
Response Time to Speed Negotiation
After Powerup
Device responding to a constant low level
driven by originator
Time after powerup when device can participate
in speed negotiation
1.25 x
tBIT
1. Guaranteed by design, not production tested.
2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.
3. Device is compatible with hold time specification as driven by SST originator.
2 x tBIT
500
Max
±1.0
±10
500
0.8 x
tBIT
0.4 x
tBIT
0.2 x
tBIT
0.5 x
tBITM
2 x tBIT
0.4
Unit
mA
mA
mV
pp
ms
ms
ms
ms
ms
ms
ms
ms
http://onsemi.com
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