ADXL312 View Datasheet(PDF) - Analog Devices
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Description
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ADXL312 Datasheet PDF : 32 Pages
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ADXL312
I2C
With CS tied high to VDD I/O, the ADXL312 is in I2C mode,
requiring a simple 2-wire connection as shown in Figure 26.
The ADXL312 conforms to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in Table 10 and
Table 11 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 27. With the ALT ADDRESS pin
high, the 7-bit I2C address for the device is 0x1D, followed by the
R/W bit. This translates to 0x3A for a write and 0x3B for a read. An
alternate I2C address of 0x53 (followed by the R/W bit) can be
chosen by grounding the ALT ADDRESS pin (Pin 7). This
translates to 0xA6 for a write and 0xA7 for a read.
VDD I/O
ADXL312
RP
CS
SDA
ALT ADDRESS
SCL
RP PROCESSOR
D IN/OUT
D OUT
Figure 26. I2C Connection Diagram (Address 0x53)
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary
for proper I2C operation. Refer to the UM10204 I2C-Bus
Specification and User Manual, Rev. 03—19 June 2007, when
selecting pull-up resistor values to ensure proper operation.
Table 10. I2C Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
Low Level Output Current (IOL)
Pin Capacitance
Test Conditions
VIN = VDD I/O
VIN = 0 V
VDD I/O < 2 V, IOL = 3 mA
VDD I/O ≥ 2 V, IOL = 3 mA
VOL = VOL, max
fIN = 1 MHz, VIN = 2.5 V
Limit1
Min
Max
0.7 × VDD I/O
−0.1
0.3 × VDD I/O
0.1
0.2 × VDD I/O
400
3
8
Unit
V
V
μA
μA
V
mV
mA
pF
1 Limits based on characterization results; not production tested.
SINGLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
ACK
DATA
STOP
ACK
MULTIPLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
ACK
DATA
ACK
DATA
STOP
ACK
SINGLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
START1
ACK
SLAVE ADDRESS + READ
ACK
DATA
NACK STOP
MULTIPLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
START1
ACK
SLAVE ADDRESS + READ
ACK
DATA
ACK
DATA
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 27. I2C Device Addressing
NACK STOP
Rev. 0 | Page 15 of 32
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