AGM2416B View Datasheet(PDF) - AZ Displays
Part Name
Description
Manufacturer
AGM2416B Datasheet PDF : 12 Pages
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AZ DISPLAYS, INC.
AGM2412B
3.1 Pin Description
Segment Pin
Pin No. Symbol
Function Description
1
V0L Bias power supply pins for LCD drive voltage
2
V12L
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that VSS • • V5 < V43 < V12 < V0.
3
V34L
ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and
4
V5L
supply regular voltage which is assigned by specification for each power pin
5
VSS
Ground
6
VSS
7
VDD
Logic power supply
8
VDD
9
DBLKB
Use as contrast control, use PWM signal as input. Connect to VDD for no
contrast control.
10
D0
11
D1
Data bus
12
D2
13
D3
14
XCK
Clock input pin for taking display data
* Data is read at the falling edge of the clock pulse.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
When set to VSS level "L", the LCD drive output pins (Y1-Y240) are set to level
Vss.
15
DOFFB
When set to "L", the contents of the line latch are reset, but the display data
are read in the data latch regardless of the condition of DISPOFF. When the
DISPOFF function is canceled, the driver outputs non-select level (V12 or V43),
then outputs the contents of the data latch at the next falling edge of the LP. At
that time, if DISPOFF removal time does not correspond to what is shown in AC
characteristics, it can not output the reading data correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
16
LP
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
17
FR
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line
latch output signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to VSS level "L", 8-bit parallel input mode is set.
18
MD
When set to VDD level "H", 4-bit parallel input mode is set.
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD
DRIVE OUTPUT PINS" in Functional Operations.
19
V5R Bias power supply pins for LCD drive voltage
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