AK4394 View Datasheet(PDF) - Asahi Kasei Microdevices
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AK4394 Datasheet PDF : 26 Pages
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ASAHI KASEI
[AK4394]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4394, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. The sampling speed is set by DFS0/1(Table 1). The sampling rate (LRCK), CKS0/1/2
and DFS0/1 determine the frequency of MCLK (Table 2). In parallel mode, since DFS1 is always “0”, the quad speed
mode can not be available.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4394 is in normal operation
mode (PD = “H”). If these clocks are not provided, the AK4394 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4394 should be in the power-down mode
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4394 is in power-down mode
until MCLK and LRCK are input.
DFS1
0
0
1
DFS0
0
1
0
Sampling Rate (fs)
Normal Speed Mode
30kHz~54kHz
Double Speed Mode
60kHz~108kHz
Quad Speed Mode
120kHz~216kHz
Default
Table 1. Sampling Speed
Mode
0
1
2
3
4
5
6
7
CKS2
0
0
0
0
1
1
1
1
CKS1
0
0
1
1
0
0
1
1
CKS0
0
1
0
1
0
1
0
1
Normal
256fs
256fs
384fs
384fs
512fs
512fs
768fs
768fs
Double
128fs
256fs
192fs
384fs
256fs
N/A
384fs
N/A
Quad
N/A
N/A
N/A
N/A
128fs
N/A
192fs
N/A
Default
Table 2. System Clocks
Note: The master clock at quad speed supports only 128fs or 192fs.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System clock example (Normal Speed Mode)
M0081-E-00
- 11 -
1999/11
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