AK4555 View Datasheet(PDF) - Asahi Kasei Microdevices

Part Name

Description

Manufacturer

AK4555

Low Power & Small Package 20bit ∆Σ CODEC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4555]

„ Power-down & Reset

The ADC and DAC of AK4555 are placed in the power-down mode by bringing each power down pin, PWADN,

PWDAN = “L” independently and each digital filter is also reset at the same time. These resets should always be done

after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the

output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC

operation. Figure 5 shows the power-up sequence when the ADC is powered up before the DAC power-up.

PWADN

ADC Internal

State

PWDAN

Normal Operation

Power-down

2081/fs

Init Cycle

Normal Operation

DAC Internal

State

ADC In

(Analog)

ADC Out

(Digital)

DAC In

(Digital)

DAC Out

(Analog)

Normal Operation

Power-down

Normal Operation

GD

GD

Idle Noise

GD

“0”data

“0”data

Idle Noise

GD

Clock In

MCLK,LRCK,SCLK

External

Mute

The clocks may be stopped.

Mute ON

Figure 5. Power-up Sequence

MS0363-E-01

- 11 -

2005/08

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