MCM72JG32 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MCM72JG32
Motorola => Freescale
MCM72JG32 Datasheet PDF : 16 Pages
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DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM72JG32–66
MCM72JG64–66
Parameter
Symbol
Min
Max
Unit Notes
Cycle Time
tKHKH
15
—
ns
Clock Access Time
tKHQV
—
7
ns
5
Output Enable to Output Valid
tGLQV
—
5
ns
Clock High to Output Active
tKHQX1
2
—
ns
Clock High to Output Change
tKHQX2
2
—
ns
Output Enable to Output Active
tGLQX
1
—
ns
Output Disable to Q High–Z
tGHQZ
—
6
ns
6
Clock High to Q High–Z
tKHQZ
2
6
ns
Clock High Pulse Width
tKHKL
5
—
ns
Clock Low Pulse Width
tKLKH
5
—
ns
Setup Times:
Address tAVKH
2.5
Address Status tADSVKH
Data In tDVKH
Write tWVKH
Address Advance tADVVKH
Chip Enable tEVKH
—
ns
7
Hold Times:
Address tKHAX
0.5
Address Status tKHADSX
Data In tKHDX
Write tKHWX
Address Advance tKHADVX
Chip Enable tKHEX
—
ns
7
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and
ADSP high for the setup and hold times.
3. All read and write cycle timings are referenced from CLK or COE.
4. COE is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 amd Pentium external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested.
At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever ADSP or
CADS is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or CADS is low) to remain
enabled.
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
9
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