GVT71256D36T-4.4 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
GVT71256D36T-4.4 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
256K X 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T, 5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47, 48,
49, 50
92 (T Version)
43 (TA Version)
5L
93
5G
94
3G
95
3L
96
4M
87
4H
88
4K
89
4E
98
2B
97
- (not available for
PBGA)
4F
92 (for TA Version
only)
86
4G
83
4A
84
4B
85
3R
31
7T
64
Name
A0
A1
A
BWa
BWb
BWc
BWd
BWE
GW
CLK
CE
CE2
CE2
OE
ADV
ADSP
ADSC
MODE
ZZ
Type
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses associ-
ated with A0 and A1, during burst cycle and wait cycle.
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and
HIGH for a READ cycle. BWa controls DQa. BWb con-
trols DQb. BWc controls DQc. BWd controls DQd. Data
I/O are high impedance if either of these inputs are LOW,
conditioned by BWE being LOW.
Input-
Write Enable: This active LOW input gates byte write
Synchronous operations and must meet the set-up and hold times
around the rising edge of CLK.
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit
WRITE to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the
rising edge of CLK.
Input-
Synchronous
Clock: This signal registers the addresses, data, chip
enables, write control, and burst control inputs on its ris-
ing edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
Input-
Chip Enable: This active HIGH input is used to enable
Synchronous the device.
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device. Not available for B and T package versions.
Input
Output Enable: This active LOW asynchronous input en-
ables the data output drivers.
Input-
Address Advance: This active LOW input is used to con-
Synchronous trol the internal burst counter. A HIGH on this pin gener-
ates wait cycle (no address advance).
Input-
Synchronous
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to
be registered and a READ cycle is initiated using the new
address.
Input-
Synchronous
Address Status Controller: This active LOW input caus-
es the device to be deselected or selected along with
new external address to be registered. A READ or
WRITE cycle is initiated depending upon write control
inputs.
Input-
Static
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Input-
Snooze: This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal opera-
tion, this input has to be either LOW or NC (No Connect).
5
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