GVT71256D36T-4.4 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
GVT71256D36T-4.4 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
256K X 36 Pin Descriptions (continued)
X36 PBGA Pins
(a) 6P, 7P, 7N, 6N,
6M, 6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E, 2F,
1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L,
2M, 1N, 2N, 1P, 2P
2U
3U
4U
5U
4C, 2J, 4J, 6J, 4R
3D, 5D, 3E, 5E, 3F, 5F,
3H, 5H, 3K, 5K, 3M,
5M, 3N, 5N, 3P, 5P
1A, 7A, 1F, 7F, 1J, 7J,
1M, 7M, 1U, 7U
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
X36 QFP Pins
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
9, 12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
38
39
43
for B and T version
42
for B and T version
15, 41, 65, 91
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
4, 11, 20, 27, 54,
61, 70, 77
14, 16, 66
38, 39, 42 for TA
Version
Name
DQa
DQb
DQc
DQd
TMS
TDI
TCK
TDO
VCC
VSS
VCCQ
NC
Type
Input/
Output
Description
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not avail-
able for TA package version.
Output
Supply
Ground
IEEE 1149.1 test output. LVTTL-level output. Not avail-
able for TA package version.
Core power Supply: +3.3V –5% and +10%
Ground: GND.
I/O Supply Output Buffer Supply: +2.5V or +3.3V.
-
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS.
512K X 18 Pin Descriptions
X18 PBGA Pins
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
5T, 6T
5L
3G
X18 QFP Pins
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49, 50
92 (T Version)
43 (TA Version)
93
94
Name
A0
A1
A
BWa
BWb
4M
87
BWE
4H
88
GW
4K
89
CLK
4E
98
CE
Type
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet
the set up and hold times around the rising edge of CLK.
The burst counter generates internal addresses associ-
ated with A0 and A1, during burst cycle and wait cycle.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a
WRITE cycle and HIGH for a READ cycle. BWa controls
DQa. BWb controls DQb. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE be-
ing LOW.
Write Enable: This active LOW input gates byte write op-
erations and must meet the set-up and hold times around
the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit
WRITE to occur independent of the BWE and WEn lines
and must meet the set-up and hold times around the ris-
ing edge of CLK.
Clock: This signal registers the addresses, data, chip en-
ables, write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
6
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