IDT7MPV6255 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT7MPV6255 Datasheet PDF : 7 Pages
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IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6256 – 512KB PIPELINED BURST VERSION
COMMERCIAL TEMPERATURE RANGE
WE#0
WE#1
WE#2
WE#3
CLK1
WE#4
WE#5
WE#6
WE#7
CLK0
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
A13 - A28 16
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
32
DH0-31
32
DL0-31
WE#0
WE#1
WE#2
WE#3
CLK1
WE#4
WE#5
WE#6
WE#7
CLK0
SRAM OE#1
SRAM ADS#1
CNT EN#1
STANDBY
BURST MODE
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
32
DH0-31
32
DL0-31
A13 - A26 14
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK2
16K x 12
Tag Field
16K x 2
Status
12
A1 - A12
TMATCH
DIRTYOUT
PD0
PD1
PD2
PD3
drw 03
CAPACITANCE (IDT7MPV6253 )(1)
(TA = +25°C, f = 1.0 MHz)
Symbol Parameter(1)
CIN1
Input Capacitance
(Address)
CIN2
Input Capacitance
(ADDR0-1)
CIN3
Input Capacitance
(OE#)
CIN4
Input Capacitance
(WE#, TWE#)
CI/O I/O Capacitance
Condition Max.
VIN = 0V
15
VIN = 0V
25
VIN = 0V
45
VIN = 0V
8
VOUT = 0V
10
NOTES:
1. These parameters are guaranteed by design but not tested.
Unit
pF
pF
pF
pF
pF
tbl 05
CAPACITANCE (IDT7MPV6255/56 )(1)
(TA = +25°C, f = 1.0 MHz)
Symbol Parameter(1)
CIN1
Input Capacitance
(Address)
CIN2
Input Capacitance
(ADDR0-1)
CIN3
Input Capacitance
(OE#)
CIN4
Input Capacitance
(WE#, TWE#)
CI/O I/O Capacitance
Condition Max.
VIN = 0V
20
VIN = 0V
—
VIN = 0V
15
VIN = 0V
8
VOUT = 0V 10/20
NOTES:
1. These parameters are guaranteed by design but not tested.
Unit
pF
pF
pF
pF
pF
tbl 06
3
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