IS6MC256K-50 View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS6MC256K-50 Datasheet PDF : 4 Pages
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IISS6M6CM25C6K256K
256KB CMOS 3.1 COASt CACHE MODULE
FOR THE INTEL PENTIUM™ CPU
IISSSSII
®
®
PRELIMINARY
FEBRUARY 1997
FEATURES
• Low-cost, card-edge low-profile (CELP)
module with 160 leads
• For Intel Pentium CPU-based systems
• Operates with Pentium CPU clock speeds up
to 66 MHz
• Separate 5V and 3.3V power supplies
• Multiple GND pins and decoupling
capacitors for maximum noise immunity
• CMOS SRAMs for low power
• Conforms to Intel COASt specification
IS6MC256K FUNCTIONAL BLOCK DIAGRAM
256KB PIPELINED BURST MODULE
+3.3V
DESCRIPTION
The ISSI IS6MC256K is a secondary cache mod-
ule designed for use with Intel Pentium CPU-
based systems. This ISSI synchronous cache
module uses IS61C632 32K x 32 pipelined syn-
chronous burst static RAMs which are mounted on
a multilayer board. In addition, this module uses a
single 5V 8-bit wide CMOS SRAM for the tag.
On-board logic, 3.3V data RAM, and a 5V tag RAM
provide an exact interface between the module
and the PC chipset. Five PD (presence detect)
input pins allow the system to determine the par-
ticular cache configuration.
ISSI's CELP 160-lead module provides space
savings that allows the customer to design addi-
tional functions into the system or to shrink the size
of the motherboard.
CWE0
CWE1
CWE2
CWE3
CLK0
32K x 32
Pipelined
Burst
SRAM
D7-D0
D15-D8
D23-D16
D31-D24
All inputs and outputs are TTL-compatible. Mul-
tiple GND pins and on-board decoupling capaci-
tors provide maximum protection from noise.
CWE4
CWE5
CWE6
CWE7
CCS
COE
ADSP
CADS
CADV
GWE
BWE
ECS1
A3
A4
A17-A5
TWE
32K x 32
Pipelined
Burst
SRAM
8K x 8
TAG SRAM
D39-D32
D47-D40
D55-D48
D63-D56
PD0
PD1
PD2
PD3
PD4
ECS2
PRESENCE DETECT TABLE
PD4 PD3 PD2 PD1 PD0 MODULE
NC NC NC NC NC No Cache Present
GND NC GND NC NC IS6MC256K
+5V
TIO7-TIO0
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
SR004-1B-297
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