MPC2104PDG66 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2104PDG66

256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

Motorola => Freescale 

TAG RAM

RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)

TCLR

L

CLK

L–H

TWE

H

TAG0 – TAG11

High–Z

DIRTYOUT

L(3)

L

L–H

L

—

—

NOTES:

1. H = VIH, L = VIL, X = don’t care, — = undefined.

2. TG is X for this table.

3. These are output states.

MATCH

L(3)

—

Operation

Reset Status

Not Allowed

POWER

Active

—

READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)

TG

TWE

CLK

TAG0 – TAG11 VALIDIN

L

H

X

Dout

—

H

X

X

High–Z

—

DIRTYIN

—

—

DIRTYOUT

Dout

—

MATCH

Dout

—

Operation

Read Tag I/O

Tag I/O Disable

WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)

TG

TWE

CLK

TAG0 – TAG11 VALIDIN DIRTYIN DIRTYOUT MATCH

H

L

L–H

Din

L

L

L–H

—

—

—

—

L

—

—

—

—

NOTES:

1. H = VIH, L = VIL, X = don’t care, — = undefined.

2. This table applies when RESET and PWRDN are high.

3. Dout in this case is the same as Din. The input data is written through to the outputs during the write operation.

Operation

Write Tag I/O

Not Allowed

MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)

TG

TWE

TAG0 – TAG11 VALIDIN(4) DIRTYIN(4)

MATCH

Operation

X

X

L

H

—

Dout

—

—

Dout

—

—

L

Selected

Read Tag I/O

H

L

Din

Din

Din

L

Write Tag I/O, Status Bits

H

H

TAGin

L

—

L

Invalid Data — Dedicated Status Bits

H

H

TAGin

H

—

H

Match — Dedicated Status Bits

NOTES:

1. H = VIH, L = VIL, X = don’t care, — = undefined.

2. M = high if TAGin equals the memory contents at the address; M = low if TAGin does not equal the contents at that address.

3. PWRDN and RESET are high for this table. GS and CLK are X.

4. This column represents the stored memory cell data for the given status bit at the selected address.

MPC2104P•MPC2105P

10

MOTOROLA FAST SRAM

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