MPC2104PDG66 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2104PDG66

256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

256KB/512KB BurstRAM™

Secondary Cache Modules for

PowerPC™ PReP/CHRP Platforms

The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide

burstable, high performance L2 cache for the PowerPC 60x microprocessor family

in conformance with the PowerPC Reference Platform (PReP) and the PowerPC

Common Hardware Reference Platform (CHRP) specifications.

The MPC2104P and MPC2105P utilize synchronous BurstRAMs. The MPC2104P

module is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs.

The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32

data RAMs. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the

2104P, a 5 V cache tag RAM configured as 8K x 14 for tag field plus 8K x 2 for valid

and dirty status bits is used. For tag bits on the 2105P, a 5 V cache tag RAM

configured as 16K x 14 for tag field plus 16K x 2 for valid and dirty status bits is used.

Bursts can be initiated with the ADS signal. Subsequent burst addresses are

generated internally to the BurstRAM by the CNTEN signal.

Write cycles are internally self–timed and are initiated by the rising edge of the clock

(CLKx) inputs. Writes are global with two inputs for reduced loading.

Presence detect pins are available for auto configuration of the cache control.

The module family pinout will support 5 V and 3.3 V components for a clear path

to lower voltage and power savings. Both power supplies must be connected.

All of these cache modules are plug and pin compatible with each other.

• PowerPC–Style Burst Counter On Chip

• Pipeline Data I/O

• Plug and Pin Compatibility

• Multiple Clock Pins for Reduced Loading

• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible

• Three State Outputs

• Buffered Addresses to Data RAMs for Reduced Loading

• Fast Module Clock Rates: Up to 66 MHz

• Fast SRAM Access Times: 9 ns for Tag RAM Match

8 ns for Data RAM

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

• 178 Pin Card Edge Module

• Burndy Connector, Part Number: ELF178KSC–3Z50

Order this document

by MPC2104P/D

MPC2104P

MPC2105P

BurstRAM is a trademark of Motorola.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 2

12/20/96

M© OMoTtoOroRla,OInLc.A19F96AST SRAM

MPC2104P•MPC2105P

1

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