MPC2104PDG66 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MPC2104PDG66
Motorola => Freescale
MPC2104PDG66 Datasheet PDF : 16 Pages
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TRUTH TABLE (See Notes 1 through 4)
Next Cycle
Address
Used
Standby
ADS0
CNTEN0
CG0 2
DHx/DLx
CWEx 2
Deselect
Begin Read
None
1
0
X
X
High–Z
X
External
0
0
X
X
High–Z
14
Continue Read
Next
X
1
0
1
High–Z
1
Continue Read
Next
X
1
0
0
DQ
1
Suspend Read
Current
X
1
1
1
High–Z
1
Suspend Read
Current
X
1
1
0
DQ
1
Begin Write
External
0
0
X
X
High–Z
0
Continue Write
Next
X
1
0
X
High–Z
0
Suspend Write
Current
X
1
1
X
High–Z
0
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. CG0 is an asynchronous signal and is not sampled by the clock CLK0. CG0 drives the bus immediately (tGLQX) following CG0 going low.
3. On write cycles that follow read cycles, CG0 must be negated prior to the start of the write cycle to ensure proper write data setup times.
CG0 must also remain negated at the completion of the write cycle to ensure proper write data hold times.
4. This READ assumes the RAM was previously deselected.
ASYNCHRONOUS TRUTH TABLE
Operation
CG0
Read
L
Read
H
Write
X
Deselected
X
Sleep
X
I/O Status
Data Out (DHx/DLx)
High–Z
High–Z
High–Z
High–Z
LINEAR BURST ADDRESS TABLE (Burst Mode = VSS)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X10
X . . . X10
X . . . X11
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (Burst Mode = VDD)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X00
X . . . X10
X . . . X11
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
MPC2104P•MPC2105P
6
MOTOROLA FAST SRAM
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