MPC2104PDG66 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2104PDG66

256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

Motorola => Freescale 

DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, VDD = 3.3 V + 10%, – 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns

Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V

Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted

SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1 and 2)

MPC2104P/5P

Parameter

Symbol

Min

Max

Unit Notes

Cycle Time

tKHKH

15

—

ns

Clock Access Time

tKHQV

—

8

ns

3

Output Enable to Output Valid

tGLQV

—

6

ns

Clock High to Output Active

tKHQX1

0

—

ns

Clock High to Output Change

tKHQX2

2

—

ns

Output Enable to Output Active

tGLQX

0

—

ns

Output Disable to Q High–Z

tGHQZ

—

8

ns

Clock High to Q High–Z

tKHQZ

2

8

ns

Clock High Pulse Width

tKHKL

5

—

ns

Clock Low Pulse Width

tKLKH

5

—

ns

Setup Times:

Address tAVKH

2.5

Address Status tSVKH

Data In tDVKH

Write tWVKH

Address Advance tBAVVKH

Chip Enable tEVKH

—

ns

4

Hold Times:

Address tKHAX

0.5

Address Status tKHTSX

Data In tKHDX

Write tKHWX

Address Advance tKHBAX

Chip Enable tKHEX

—

ns

4

NOTES:

1. All read and write cycle timings are referenced from CLK or CG0.

2. CG is a don’t care when CWEx is sampled low.

3. Maximum access times are guaranteed for all possible PowerPC external bus cycles.

4. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever ADS0

is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of

CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADS0 is low) to remain enabled.

MPC2104P•MPC2105P

8

MOTOROLA FAST SRAM

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