EBS21RC2ACNA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EBS21RC2ACNA Datasheet PDF : 15 Pages
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EBS21RC2ACNA
AC Characteristics (SDRAM device specification)
-7A
-75
Parameter
Symbol
min.
min.
max.
Unit
System clock cycle time
tCK
7.5
7.5
—
ns
CLK high pulse width
tCH
2.5
2.5
—
ns
CLK low pulse width
tCL
2.5
2.5
—
ns
Access time from CLK
tAC
—
—
5.4
ns
Data-out hold time
tOH
2.7
2.7
—
ns
CLK to Data-out low impedance
tLZ
1
1
—
ns
CLK to Data-out high impedance
tHZ
—
—
5.4
ns
Input setup time
tSI
1.5
1.5
—
ns
Input hold time
tHI
0.8
0.8
—
ns
Ref/Active to Ref/Active command period tRC
60
67.5
—
ns
Active to Precharge command period
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge
lead time
Last data into active latency
tRAS
tRCD
tRP
tDPL
tDAL
45
45
120000
ns
15
20
—
ns
15
20
—
ns
15
15
—
ns
2CLK + 15ns 2CLK + 20ns —
Active (a) to Active (b) command period tRRD
15
15
—
ns
Transition time (rise and fall)
tT
0.5
0.5
5
ns
Refresh period
(8192 refresh cycles)
tREF
—
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4V
2.0V
0.4V 0.8V
DQ
CL
tT
tT
Input Waveform and Output Load
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
1
Data Sheet E0105E50 (Ver. 5.0)
10
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