EBS21RC2ACNA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EBS21RC2ACNA Datasheet PDF : 15 Pages
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EBS21RC2ACNA
Relationship Between Frequency and Minimum Latency (SDRAM device specification)
Parameter
-7A
-75
Frequency (MHz)
133
133
133
100
tCK (ns)
7.5
7.5
7.5
10
/CAS latency
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
CL = 3
2
8
6
2
2
2
1
4
CL = 2
2
8
6
2
2
2
1
4
CL = 3
3
9
6
3
2
2
1
5
CL = 2
2
7
5
2
2
2
1
4
Self refresh exit to command input
lSEC
8
8
9
7
Precharge command to high impedance lHZP
3
2
3
2
Last data out to active command
(auto precharge) (same bank)
lAPR
1
1
1
1
Last data out to precharge (early
precharge)
lEP
–2
–1
–2
–1
Column command to column command lCCD
1
1
1
1
Write command to data in latency
lWCD
0
0
0
0
DQM to data in
lDID
0
0
0
0
DQM to data out
lDOD
2
2
2
2
CKE to CLK disable
lCLE
1
1
1
1
Register set to active command
lMRD
1
1
1
1
/CS to command disable
lCDD
0
0
0
0
Power down exit to command input
lPEC
1
1
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Data Sheet E0105E50 (Ver. 5.0)
11
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