NT256D72S4PA0GR-7K View Datasheet(PDF) - Nanya Technology

Part Name

Description

Manufacturer

NT256D72S4PA0GR-7K

184pin One Bank Registered DDR SDRAM MODULE Based on 32Mx4 DDR SDRAM

Nanya Technology 

NT256D72S4PA0GR

256MB : 32M x 72

Registered DDR SDRAM DIMM

Operating, Standby, and Refresh Currents

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;

I DD0

tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; active / read / precharge; Burst = 2;

I DD1

tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;

address and control inputs changing once per clock cycle

I DD2P

Precharge Power-Down Standby Current :

all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

I DD2N

Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE ≥ VIH(MIN) ;

tCK = tCK (MIN) ; address and control inputs changing once per clock cycle

I DD3P

Active Power-Down Standby Current : one bank active;

power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

I DD3N

Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;

CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS

inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; Burst = 2; reads; continuous burst;

I DD4R

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5;

tCK = tCK (MIN) ; IOUT = 0mA

Operating Current : one bank; Burst = 2; writes; continuous burst;

I DD4W

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5;

tCK = tCK (MIN)

I DD5 Auto-Refresh Current :

t RC = t RFC (MIN)

t RC = 15.625 µs

I DD6 Self-Refresh Current : CKE ≤ ?0.2V

1. I DD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

3. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 15.625 µs.

PC1600

2180

2450

1100

1370

1110

1730

3170

2900

3710

1113

61

PC2100

2470

Unit Notes

mA

1

2990

1100

1600

1100

mA

1

mA

1

mA

1

mA

1

2078

mA

1

4026

mA

1

2840

3940

1113

61

mA

1

mA

1,3

mA

mA

1

Preliminary 08/01

10

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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