AN217 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
AN217 Datasheet PDF : 18 Pages
| |||
AN217
SFR Definition 2.3. ADC0DECH: ADC0 Decimation Ratio Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
-
DECI10 DECI9 DECI8 00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x9B
Bits 7–3: Unused: Read = 00000b, Write = don’t care.
Bits 2–0: DECI[10:8]: ADC0 Decimation Ratio Register, Bits 10–8.
This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio deter-
mines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the ADC0DECL
register description for more information.
This SFR can only be modified when ADC0 is in IDLE mode.
SFR Definition 2.4. ADC0DECL: ADC0 Decimation Ratio Register Low Byte
R/W
DECI7
Bit7
R/W
DECI6
Bit6
R/W
DECI5
Bit5
R/W
DECI4
Bit4
R/W
DECI3
Bit3
R/W
DECI2
Bit2
R/W
DECI1
Bit1
R/W
Reset Value
DECI0 11111111
Bit0
SFR Address: 0x9A
Bits 7–0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7–0.
This register contains the low byte of the 11-bit ADC Decimation Ratio. The decimation ratio deter-
mines the number of modulator input samples used to generate a single output word from the ADC.
The ADC0 decimation ratio is defined as:
Decimation Ratio = DECI[10:0] + 1
The corresponding sampling period and output word rate of ADC0 is:
ADC0 Conversion Period = [(DECI[10:0] + 1) x 128] / MDCLK
ADC0 Output Word Rate = MDCLK / [128 x (DECI[10:0] + 1)]
The minimum decimation ratio setting is 20. Any register setting below 19 will automatically be
interpreted as 19.
Important: When using the fast filter, the decimation ratio must be divisible by 8 (DECI[2:0] =
111b).
This SFR can only be modified when ADC0 is in IDLE mode.
8
Rev. 0.2
Share Link: 