AN247 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

AN247

A CAN Bootloader for PIC18F CAN Microcontrollers

Microchip Technology 

REMAPPED MEMORY AND VECTORS

Since the hardware RESET and interrupt vectors lie

within the boot area and cannot be edited if the block is

protected, they are remapped through software to the

nearest parallel locations outside the boot block.

Remapping is simply a branch for interrupts, so PIC18F

users should note an additional latency of 2 instruction

cycles to handle interrupts. Upon RESET, there are

some boot condition checks, so the RESET latency is

an additional 10 instruction cycles (as seen in the

example source code).

Notice the memory regions do not necessarily correlate

to the physical addresses in the device (see Figure 3).

For example, EEDATA is located at F00000h; however,

in the PIC18 device, EEDATA operates as a separate

module and is not located in the device memory map.

In addition, the regions only define where the boot-

loader operates and the type of memory that it operates

on. This should not be interpreted as meaning that

writable memory is available over the entire defined

memory areas.

FIGURE 3:

BOOTLOADER MEMORY

REGIONS

Boot Program

(000h - 1FFh)

000000h

Program Memory

Config Memory

2FFFFFh

300000h

3FFFFFh

Unused

EEPROM Data

F00000h

FFFFFFh

Note: Memory areas not shown to scale.

DATA MEMORY USAGE

The last location in Data Memory of the device

(Figure 4) is reserved as a non-volatile Boot mode flag.

This location contains FFh by default, which indicates

Boot mode. Any other value in this location indicates

normal Execution mode.

AN247

FIGURE 4:

DATA MEMORY MAP

000h

EE Data

Memory

Boot Control Byte XXXh

COMMUNICATION AND CONTROL

PROTOCOL

From the functional view in Figure 1, the bootloader

looks and behaves like a hardware module. This is

mostly because the bootloader’s operation is dictated

by two “commands” derived from single bit values, as

well as a set of defined Control registers.

Basic Bootloader Commands

There are essentially two data control commands: PUT

and GET. These commands are implemented through

a single bit passed via the CAN Message Identifier field

(in this version, bit 1 of the 18-bit Extended Identifier

field); the command is PUT when the bit is ‘0’, and GET

when it is ‘1’. PUT or GET can operate on either a type

of memory or the Control register set. GET commands

are ignored if P-Mode is specified.

The CONTROL/DATA bit, also defined in the Identifier

field (in this version, bit 0 of the Extended Identifier),

indicates the destination of the frame data. When the

bit is ‘0’, the data is interpreted as Control register

content; when it is ‘1’, the data is programming data.

The bit assignments for PUT/GET and CONTROL/DATA

are arbitrary, and are defined by compile time definitions.

The user may change the locations of these bits in the

identifier as the application requires.

Control Registers

There are eight Control registers, which represent the

maximum number of bytes that can be contained in the

data field of a single CAN frame. The registers are

shown in order in Figure 5.

FIGURE 5:

CONTROL REGISTERS

Address Low

D0

Address High

D1

Address Upper D2

(Reserved)

D3

Control Bits

D4

Command

D5

Data A

D6

Data B

D7

 2003 Microchip Technology Inc.

DS00247A-page 3

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