AN504 View Datasheet(PDF) - Vishay Semiconductors
Part Name
Description
Manufacturer
AN504 Datasheet PDF : 12 Pages
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AN504
Vishay Siliconix
High-Frequency Model
The parameters that determine the frequency response of the
selected crosspoint are input capacitance and on-resistance.
Input capacitance is made up of interconnect lines on the chip,
FET capacitance, and small bond wire and interconnect
capacitances. On-resistance is made up of the three series
FETs that form the crosspoint path. DMOS FETs are very
efficient at providing low on-resistance in a small area;
however, the resistance is spread over the entire channel
length. Thus, resistance and capacitance are distributed, and
the simple lumped models of Figures 3 and 4 are inadequate
for high frequencies. Figure 6 shows a suitable model of an
“on” channel. The five-stage model is easily obtained from the
data sheet by taking on-resistance and capacitance values
and dividing them by five to obtain the element values, as
shown in Figure 6. Worst-case values are those obtained from
a one input to four output set-up condition. Note that we show
the model driven by a voltage source with zero output
impedance –– the importance of this in maximizing operating
bandwidth should not be underestimated. To generate the
data sheet frequency curves, Vishay Siliconix uses a network
analyzer to obtain Vout/Vin with respect to frequency. In this
way, the device plots are independent of source impedance.
The DG884 is a high-performance device and must be driven
by very high-performance analog buffers, such as the
Vishay Siliconix CLC111 and CLC410. The accompanying
performance curves were derived from an evaluation board
consisting of CLC111s at the inputs and gain-of-two CLC410s
at the outputs of a DG884.
A RESET command may be used as a power on reset. This will
clear the current event latches and will result in all outputs
being turned off. The RESET command operates on the
current event address latches only. This is to allow existing or
new data to be retained in the next event latches independent
of the RESET operation.
To address the device, CHIP SELECT should be set low, I/O
low, and RESET, WRITE, and SALVO all high. The
input-to-output path is selected by A0 – A3 for the input, and B0,
B1 for the output. Each addressing byte (A0 – A3) is latched into
the next event latch (selected by the B0, B1 address) by the
WRITE line going low and returning high again. This is
repeated three more times to address all four output lines. Note
that the internal logic forbids any addressing that tries to
connect two separate inputs to the same output.
Having set four input-to-output paths into the next-event
latches with four WRITE commands, the current event latches
are then simultaneously loaded by SALVO going low and
returning high.
The A0 – A3 address inputs are tri-stated when CHIP SELECT
returns to high, along with RESET, I/O, WRITE, and SALVO.
This ensures that no bus contention will occur during input
addressing or data readback when a number of devices are
connected in parallel.
VIN
R1
R2
C1
C2
R5
C5
VOUT
RL
R1 + R2 + R3 + ...Rn = rDS(on)
C1 + C2 + C3 + ...Cn = (CS + CD) (on)
FIGURE 6. Wideband On-Channel Equivalent Circuit
The DG884 has data readback built in. This useful facility
enables a form of handshaking to verify that a particular
address has been set. Data readback is enabled by the I/O line
going high and CHIP SELECT going low on the device being
interrogated.
Address A3 functions as an output turn-off command. There
are four open-drain DISABLE pins that are active low when the
particular output is off. They are designed to interface directly
with the disable pin of the CLC410 current feedback op amp.
For other uses, the DG884 DIS outputs look like 200 W to V–,
when V+ = 15 V.
The Digital Interface
The DG884 has comprehensive microprocessor interface
facilities. A brief explanation of the sequence of commands
required to set up the device follows.
www.vishay.com S FaxBack 408-970-5600
6-4
Figure 7 shows a memory mapped interface scheme for an
8085 microprocessor. From the circuit diagram, assume that
the address decode gives a base address to the DG884 of 0
N1 N2 N3 0 H, where N is a specific hex number. The A0 and
A1 address lines connected to B0 and B1 inputs, respectively,
of the DG884, map its address from 0 N1-3 0 H through to 0 N1-3
3 H (i.e., four address locations).
Document Number: 70610
05-Aug-99
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